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CD74AC245 Datasheet(PDF) 12 Page - Texas Instruments |
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CD74AC245 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 15 page ![]() 7 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 7.1 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 4.2. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 7.2 Layout 7.2.1 Layout Guidelines When using multiple-bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Section 7.2.2 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled. 7.2.2 Layout Example Vcc Unused Input Input Output Input Unused Input Output Figure 7-1. Layout Diagram CD54AC245, CD74AC245, CD54ACT245, CD74ACT245 SCHS245D – NOVEMBER 1998 – REVISED APRIL 2024 www.ti.com 12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: CD54AC245 CD74AC245 CD54ACT245 CD74ACT245 |
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