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DIGITAL INPUTS AND TIMING

Digital Inputs

DA[11:0]

DB[11:0]

SLEEP

CLKA/B

WRTA/B

Internal

Digital In

DVDD

DGND

GSET

MODE

Internal

Digital In

DVDD

DGND

Input Interfaces

DAC5662-EP

SGLS340A – JUNE 2006 – REVISED OCTOBER 2006

The data input ports of the DAC5662 accept a standard positive coding with data bit D11 being the most

significant bit (MSB). The converter outputs are specified to support a clock rate up to 200 MSPS. The best

performance is typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle

may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within

their specified limits.

All digital inputs of the DAC5662 are CMOS compatible. Figure 16 and Figure 17 show schematics of the

equivalent CMOS digital inputs of the DAC5662. The 12-bit digital data input follows the offset positive binary

coding scheme. The DAC5662 is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.

Figure 16. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor

Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor

The DAC5662 features two operating modes selected by the MODE pin (see Table 1).

•

For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own

separate data input bus, clock input, and data write signal (data latch-in).

•

In single-bus interleaved mode, the data should be presented interleaved at the I-channel input bus. The

Q-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.

Table 1. Operating Modes

MODE PIN

Mode pin connected to DGND

Mode pin connected to DVDD

BUS INPUT

Single-bus interleaved mode, clock and write input equal for both DACs Dual-bus mode, DACs operate independently

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