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APPLICATION INFORMATION

Theory of Operation

DAC Transfer Function

I

OUTFS +

I

OUT1 )

I

OUT2

(1)

I

OUT1 +

I

OUTFS

Code

4096

(2)

I

OUT2 +

I

OUTFS

4095 *

Code

4096

(3)

I

OUTFS +

32

I

REF +

32

V

REF

R

SET

(4)

V

OUT1 +

I

OUT1

R

LOAD

(5)

V

OUT2 +

I

OUT2

R

LOAD

(6)

DAC5662-EP

SGLS340A – JUNE 2006 – REVISED OCTOBER 2006

The architecture of the DAC5662 uses a current steering technique to enable fast switching and high update

rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to

deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches

each time the DAC is updated and a corresponding output current is formed by steering all currents to either

output summing node, IOUT1 and IOUT2. The complementary outputs deliver a differential output signal, which

improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),

and double the peak-to-peak output signal swing by a factor of two, compared to single-ended operation.

The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic

performance (SFDR) and DNL. The current outputs maintain a high output impedance of greater than 300 k

Ω.

When pin 42 (GSET) is high (one resistor mode), the full-scale output current for both DACs is determined by

the ratio of the internal reference voltage (1.2 V) and an external resistor (RSET) connected to BIASJ_A. When

GSET is low (two resistor mode), the full-scale output current for each DACs is determined by the ratio of the

internal reference voltage (1.2 V) and separate external resistors (RSET) connected to BIASJ_A and BIASJ_B.

The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can

range from 2 mA to 20 mA, depending on the value of RSET.

The DAC5662 is split into a digital and an analog portion, each of which is powered through its own supply pin.

The digital section includes edge-triggered input latches and the decoder logic, while the analog section

comprises the current source array with its associated switches, and the reference circuitry.

Each of the DACs in the DAC5662 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale

output current, IOUTFS, is the summation of the two complementary output currents:

The individual output currents depend on the DAC code and can be expressed as:

where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the

reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).

In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage

develops at each output according to:

The value of the load resistance is limited by the output compliance specification of the DAC5662. To maintain

specified linearity performance, the voltage for IOUT1 and IOUT2 should not exceed the maximum allowable

compliance range.

18

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