WM8994ECSSLASHR datasheet(225/363 Pages) CIRRUS

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WM8994

Rev 4.6

225

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

19 (13h)

R57 (39h)

6 bits

Bit 1

27h

BIAS_SRC = 1

STARTUP_BIAS_ENA = 1

VMID_BUF_ENA = 1

VMID_RAMP[1:0] = 10b

(delay = 0.5625ms)

20 (14h)

R56 (38h)

1 bit

Bit 6

01h

HPOUT2_IN_ENA = 1

(delay = 0.5625ms)

21 (15h)

R31 (1Fh)

1 bit

Bit 5

00h

HPOUT2_MUTE = 0

(delay = 0.5625ms)

22 (16h)

R1 (01h)

1 bit

Bit 11

01h

HPOUT2_ENA = 1

(delay = 0.5625ms)

23 (17h)

R1 (01h)

3 bits

Bit 0

03h

BIAS_ENA = 1

VMID_SEL[1:0] = 01b

(delay = 256.5ms)

24 (18h)

R57 (39h)

1 bit

Bit 1

00h

BIAS_SRC = 0

(delay = 0.5625ms)

Table 126 Earpiece Start-Up Default Sequence

Line Output Start-Up

The Line Output Start-Up sequence can be initiated by writing 8119h to Register 272 (0110h). This

single operation starts the Control Write Sequencer at Index Address 25 (19h) and executes the

sequence defined in Table 127.

This sequence takes approximately 517ms to run.

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

25 (19h)

R56 (38h)

2 bits

Bit 4

03h

LINEOUT2_DISCH = 1

LINEOUT1_DISCH = 1

(delay = 0.5625ms)

26 (1Ah)

R57 (39h)

6 bits

Bit 1

27h

BIAS_SRC = 1

STARTUP_BIAS_ENA = 1

VMID_BUF_ENA = 1

VMID_RAMP[1:0] = 10b

(delay = 0.5625ms)

27 (1Bh)

R56 (38h)

1 bit

Bit 7

01h

LINEOUT_VMID_BUF_ENA = 1

(delay = 0.5625ms)

28 (1Ch)

R3 (03h)

4 bits

Bit 10

0Fh

LINEOUT2P_ENA = 1

LINEOUT2N_ENA = 1

LINEOUT1P_ENA = 1

LINEOUT1N_ENA = 1

(delay = 0.5625ms)

29 (1Dh)

R56 (38h)

2 bits

Bit 4

00h

LINEOUT2_DISCH = 0

LINEOUT1_DISCH = 0

(delay = 0.5625ms)

30 (1Eh)

R1 (01h)

3 bits

Bit 0

03h

BIAS_ENA = 1

VMID_SEL = 01b

(delay = 512.5ms)

31 (1Fh)

R57 (39h)

1 bit

Bit 1

00h

BIAS_SRC = 0

(delay = 0.5625ms)

WM8994ECS/R Datasheet(PDF) 225 Page - Cirrus Logic

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