LMH0366

SNAS585D – APRIL 2012 – REVISED APRIL 2013

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Loop Filter

The reclocker uses an external loop filter, which consists of a 56 nF capacitor connected between the LF1 and

LF2 pins.

Enable

The ENABLE input is used to enable or disable the LMH0366. Disabling the device powers down the output

drivers and most of the internal circuitry in order to minimize the power dissipation. While in the disabled state,

the SPI and input signal detection remain active. The external clock reference circuitry (XTAL_IN and

XTAL_OUT) also remains active, allowing the 27 MHz reference clock signal to be generated and passed on to

additional reclockers. ENABLE is active high and this pin has an internal pullup to enable the LMH0366 by

default.

General Purpose Input/Output Pins (GPIO[3:0])

The LMH0366 has two pins that can be configured through the SPI to provide direct access to certain register

values via a dedicated pin. For example, if a particular application requires fast access to the condition of losing

the input signal to the reclocker, the signal detect status bit could be routed directly to an external pin where it

might generate an interrupt for the host processor. The GPIO pins can be configured as inputs or outputs. When

used as inputs, the GPIO pins can be configured with a pullup resistor, a pulldown resistor, or no biasing at all.

The two GPIO pins, pins 24 and 1, originally function as the RATE0 and RATE1 inputs, respectively. To use

these pins as GPIOs, their default functions must first be overridden. Setting register 0x1D bit 0

(RATE_SEL_OV) overrides the use of these pins as RATE0 and RATE1 and allows the rate selection to be

controlled by register 0x1C bits 1:0 (RATE_SEL), freeing pins 24 and 1 to be used as GPIO0 and GPIO1.

The two GPIO pins are controlled by registers 0x04 (GPIO0 Control) and 0x05 (GPIO1 Control).

For each of these GPIO control registers, bits 7:4 control the output mode, and can select between general

purpose output and signal detect. When the GPIO is configured as an input, this mode selection has no effect.

Bits 3 and 2 select either a pullup or pulldown resistor for when the GPIO is operating as an input. Do not enable

the pullup and pulldown resistor simultaneously. When the GPIO is operating as an output, neither the pullup nor

the pulldown resistor should be enabled.

Bits 1 and 0 enable or disable the input and output buffers. If the GPIO is used as an output, the output buffer

must be enabled and the input buffer must be disabled. If the GPIO is used as an input, the input buffer must be

enabled and the output must be disabled. Do not enable both the input and output buffers simultaneously.

If the GPIO pins are configured as inputs, then the input values on each of the four GPIOs can be monitored via

register 0x03 bits 1:0 (GPIO_IN_VAL). If the GPIO pins are configured as general purpose output pins, then the

values written to register 0x08 bits 1:0 (GPIO_OUT_VAL) will appear on the respective GPIO pins.

Eye Opening Monitor (EOM)

The LMH0366 includes an eye opening monitor for analyzing the quality of the incoming signal, accessible via

the SPI. It analyzes the eye opening with 64 horizontal time points and 64 vertical voltage points, with 6-bit phase

DAC control for the horizontal coordinates and 6-bit voltage DAC control for the vertical coordinates.

The eye opening monitor can be used to measure the eye shape using either the normal or fast EOM modes. It

can also be used to quickly determine the width and height of the eye opening.

Eye Opening Monitor Configuration

For all modes, the eye opening monitor must first be enabled by clearing register 0x14 bit 4 (EOM_PD).

The LMH0366 must be locked to the incoming data rate for eye opening monitor operation.

The input signal to the eye opening monitor is equalized by default, but register 0x14 bit 1 (MUX2_EQ_SEL) can

be used to select between non-equalized or equalized data.

The output eye monitor is configured for HD input signals by default. When analyzing SD input signals, it is

recommended to set register 0x11 bit 2 (EOM_SEL_SD) to enable SD eye monitor mode. For 3G input signals, it

is recommended to set register 0x22 bit 6 (EOM_SEL_3G) to enable 3G eye monitor mode.

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