M58LR128GT datasheet(27/84 Pages) STMICROELECTRONICS

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M58LR128GT, M58LR128GB

CONFIGURATION REGISTER

The Configuration Register is used to configure

the type of bus access that the memory will per-

form. Refer to Read Modes section for details on

read operations.

The Configuration Register is set through the

Command Interface using the Set Configuration

device is configured for asynchronous read (CR15

= 1). The Configuration Register bits are described

in Table 11. They specify the selection of the burst

length, burst type, burst X latency and the read op-

eration. Refer to Figures 6 and 7 for examples of

synchronous burst configurations.

Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch be-

tween Asynchronous and Synchronous Read op-

erations.

When the Read Select bit is set to ’1’, read opera-

tions are asynchronous; when the Read Select bit

is set to ’0’, read operations are synchronous.

Synchronous Burst Read is supported in both pa-

rameter and main blocks and can be performed

across banks.

On reset or power-up the Read Select bit is set to

’1’ for asynchronous access.

X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous

Read operations to set the number of clock cycles

between the address being latched and the first

data becoming available.

For correct operation the X-Latency bits can only

assume the values in Table 11., Configuration

Table 10. shows how to set the X-Latency param-

eter, taking into account the speed class of the de-

vice and the Frequency used to read the Flash

memory in Synchronous mode.

Table 10. X-Latency Settings

Wait Polarity Bit (CR10)

The Wait Polarity bit is used to set the polarity of

the Wait signal used in Synchronous Burst Read

mode. During Synchronous Burst Read mode the

Wait signal indicates whether the data output are

valid or a WAIT state must be inserted.

When the Wait Polarity bit is set to ‘0’ the Wait sig-

nal is active Low. When the Wait Polarity bit is set

to ‘1’ the Wait signal is active High.

Data Output Configuration Bit (CR9)

The Data Output Configuration bit is used to con-

figure the output to remain valid for either one or

two clock cycles during synchronous mode.

When the Data Output Configuration Bit is ’0’ the

output data is valid for one clock cycle, when the

Data Output Configuration Bit is ’1’ the output data

is valid for two clock cycles.

The Data Output Configuration must be config-

ured using the following condition:

■

tK > tKQV + tQVK_CPU

where

■

tK is the clock period

■

tQVK_CPU is the data setup time required by

the system CPU

■

tKQV is the clock to data valid time.

If this condition is not satisfied, the Data Output

Configuration bit should be set to ‘1’ (two clock cy-

cles). Refer to Figure 6., X-Latency and Data Out-

put Configuration Example.

Wait Configuration Bit (CR8)

The Wait Configuration bit is used to control the

timing of the Wait output pin, WAIT, in Synchro-

nous Burst Read mode.

When WAIT is asserted, Data is Not Valid and

when WAIT is de-asserted, Data is Valid.

When the Wait Configuration bit is Low (set to ’0’)

the Wait output pin is asserted during the WAIT

state. When the Wait Configuration bit is High (set

to ’1’), the Wait output pin is asserted one data cy-

cle before the WAIT state.

Burst Type Bit (CR7)

The Burst Type bit determines the sequence of ad-

dresses read during Synchronous Burst Reads.

The Burst Type bit is High (set to ’1’), as the mem-

ory outputs from sequential addresses only.

See Table 12., Burst Type Definition, for the se-

quence of addresses output from a given starting

address in sequential mode.

Valid Clock Edge Bit (CR6)

The Valid Clock Edge bit, CR6, is used to config-

ure the active edge of the Clock, K, during syn-

fmax

tKmin

X-Latency (Mins)

30MHz

33ns

40MHz

25ns

54MHz

19ns

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