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HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE

Normalized Frequency − y fS/1000

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

0.0

0.1

0.2

0.3

0.4

G028

Normalized Frequency − y fS/1000

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

G029

PRINCIPLES OF OPERATION

THEORY OF OPERATION

PCM1804

SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)

STOP-BAND CHARACTERISTICS

PASS-BAND CHARACTERISTICS

Figure 28.

Figure 29.

The PCM1804 consists of a band-gap reference, a delta-sigma modulator with full-differential architecture for

L-channel and R-channel, a decimation filter with a high-pass filter, and a serial interface circuit. Figure 30

illustrates the total architecture of the PCM1804. An on-chip, high-precision reference with 10-

μF external

capacitor(s) provides all the reference voltage needed in the PCM1804, and it defines the full-scale voltage range

of both channels. Full-differential architecture provides a wide dynamic range and excellent power-supply

rejection performance. The input signal is sampled at

×128, ×64, and ×32 oversampling rates according to the

overasmpling ratio control, OSR[0:2]. The single rate, dual rate, and quad rate eliminate the external sample-hold

amplifier. Figure 31 illustrates how for each oversampling ratio the PCM1804 decimates the modulator output

down to PCM data when the modulator is running at 6.144 MHz. The delta-sigma modulation randomizes the

modulator outputs and reduces the idle tone level. The oversampled data stream from the delta-sigma modulator

is converted to a 1-fS, 24-bit digital signal, while removing high-frequency noise components using a decimation

filter. The dc components of the signal are removed by the HPF, and the HPF output is converted to a

time-multiplexed serial signal through the serial interface, which provides flexible serial formats and master/slave

modes. The PCM1804 also has a DSD output mode. The PCM1804 can output the signal directly from the

modulators to DSDL (pin 16) and DSDR (pin 15).

16

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