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PCM1804DBRG4 Datasheet(PDF) 23 Page - Texas Instruments |
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PCM1804DBRG4 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 39 page ![]() www.ti.com BCK LRCK DATA tw(BCKH) tw(BCKL) t(CKLR) t(LRCP) t(BCKP) t(CKDO) t(LRDO) 0.5 VDD 0.5 VDD 0.5 VDD T0018-03 PCM1804 SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 PARAMETERS MIN TYP MAX UNIT t(BCKP) BCK period 1/(64 fS) (3) tw(BCKH) BCK pulse duration, HIGH 32 ns tw(BCKL) BCK pulse duration, LOW 32 ns t(CKLR) Delay time, BCK falling edge to LRCK valid –5 15 ns t(LRCP) LRCK period 1/fS t(CKDO) Delay time, BCK falling edge to DATA valid –5 15 ns t(LRDO) Delay time, LRCK edge to DATA valid –5 15 ns tr Rising time of all signals(1)(2) 10 ns tf Falling time of all signals(1)(2) 10 ns (1) Rising and falling times are measured from 10% to 90% of IN/OUT signal swing. (2) Load capacitance of all signals is 10 pF. (3) t(BCKP) is fixed at 1/(64 fS) in case of master mode. Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs) Copyright © 2001–2007, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link(s): PCM1804 |
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