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tw(BCKH)

tw(BCKL)

t(CKDO)

t(BCKP)

0.5 VDD

0.5 VDD

DSDBCK

DSDL

DSDR

T0053−01

SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM FOR PCM

HIGH-PASS FILTER (HPF) BYPASS CONTROL FOR PCM

PCM1804

SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007

PARAMETERS

MIN

TYP

MAX

UNIT

t(BCKP)

DSDBCK period

354

ns

tw(BCKH)

DSDBCK pulse duration, HIGH

177

ns

tw(BCKL)

DSDBCK pulse duration, LOW

177

ns

t(CKDO)

Delay time DSDBCK falling edge to DSDL, DSDR valid

–5

15

ns

tr

Rising time of all signals(1)(2)

10

ns

tf

Falling time of all signals(1)(2)

10

ns

(1)

Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.

(2)

Load capacitance of DSDBCK/DSDL/DSDR signal is 10 pF.

Figure 40. Audio Data Interface Timing for DSD (Master Mode Only)

In slave mode, the PCM1804 operates under LRCK synchronized with the system clock SCKI. The PCM1804

does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of

LRCK and SCKI.

If the relationship between LRCK and SCKI changes more than ±6 BCK during one sample period due to LRCK

or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced into BPZ code until

resynchronization between LRCK and SCKI is completed.

In case of changes less than ±5 BCK, resynchronization does not occur and the previously described digital

output control and discontinuity do not occur.

Figure 41 illustrates ADC digital output for loss of synchronization and resynchronization. During undefined data,

the PCM1804 may generate some noise in the audio signal. Also, the transitions of normal to undefined data and

undefined or zero data to normal cause a discontinuity of data on the digital output. This can generate noise in

the audio signal. In master mode, synchronization loss never occurs.

The built-in function for dc component rejection can be bypassed by BYPAS (pin 12) control. In bypass mode,

the dc component of the input analog signal and the internal dc offset are also converted and output in the digital

output data.

HPF Bypass Control

BYPAS PIN

HPF MODE

Low

Normal (high-pass) mode

High

Bypass (through) mode

Copyright © 2001–2007, Texas Instruments Incorporated

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