PCM1850

PCM1851

SLES108 − MARCH 2004

www.ti.com

27

TYPICAL CIRCUIT CONNECTION DIAGRAM

The following figure illustrates a typical circuit connection diagram for six stereo inputs and an analog monitor.

23

22

21

20

19

12

VINR2

VINL2

VINR1

VINL1

MOUTL

MOUTR

RST

TEST1

VREFS

VREF1

VREF2

Vcc

AGND

MS (ADR)(1)

MC (SCL)(1)

MD (SDA)(1)

24

18

3

4

5

6

7

8

17

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

+

C16

C17

C15 C14 C13 C12 C11 C10

+++

+++

+

Analog Input/Output

+

C9

+

C8

+

C7

+

C6

+

C19

+

C18

+

C5

+

C4

+

C3

+

C1

+5 V

0 V

C2

+

3.3 V

Control

Audio Data Processor

PCM1850/1851

(1) PCM1850 (PCM1851)

NOTE: C1, C2: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended, depending on layout and power supply.

C3, C4, C5: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended.

C6 – C17: A 0.33-µF capacitor gives a 2.9-Hz (τ = 0.33 µF × 169 kΩ) typical cutoff frequency at the HPF input in normal operation, and it

requires power-on settling time with a 56-ms time constant in the power-on initialization period. Cutoff frequency and time constant depend

on PGA gain. Cutoff frequency varies from 2.4 Hz to 8.5 Hz for 0.33

µF. Dc-coupled input is inhibited for the analog input, VINL[1:6] and

VINR[1:6].

C18–C19: A 2.2-µF capacitor with a 10-kΩ load gives a 7.2-Hz cutoff frequency.