STM32F205RFT6 datasheet(142/184 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F20xxx

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DocID15818 Rev 15

PC Card/CompactFlash controller waveforms and timings

Figure 65 through Figure 70 represent synchronous waveforms, with Table 80 and Table 81

providing the corresponding timings. The results shown in these table are obtained with the

following FSMC configuration:

•

COM.FSMC_SetupTime = 0x04;

•

COM.FSMC_WaitSetupTime = 0x07;

•

COM.FSMC_HoldSetupTime = 0x04;

•

COM.FSMC_HiZSetupTime = 0x00;

•

ATT.FSMC_SetupTime = 0x04;

•

ATT.FSMC_WaitSetupTime = 0x07;

•

ATT.FSMC_HoldSetupTime = 0x04;

•

ATT.FSMC_HiZSetupTime = 0x00;

•

IO.FSMC_SetupTime = 0x04;

•

IO.FSMC_WaitSetupTime = 0x07;

•

IO.FSMC_HoldSetupTime = 0x04;

•

IO.FSMC_HiZSetupTime = 0x00;

•

TCLRSetupTime = 0;

•

TARSetupTime = 0;

In all timing tables, the THCLK is the HCLK clock period.

td(CLKL-

NADVL)

FSMC_CLK low to FSMC_NADV low

td(CLKL-

NADVH)

FSMC_CLK low to FSMC_NADV high

td(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x=16…25)

td(CLKL-AIV)

FSMC_CLK low to FSMC_Ax invalid (x=16…25)

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low

td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high

td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low

td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high

1. CL = 30 pF.

2. Guaranteed by characterization results, not tested in production.

Table 79. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued)

Symbol

Parameter

Min

Max

Unit

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