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STM32L4R9ZIT6 Datasheet(PDF) 59 Page - STMicroelectronics |
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STM32L4R9ZIT6 Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 306 page ![]() DocID030321 Rev 3 59/306 STM32L4R5xx, STM32L4R7xx and STM32L4R9xx Functional overview 64 • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. • Interruption sources when enabled: –Errors. – FIFO requests. • DMA interface with two dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. 3.37 Controller area network (CAN) The CAN is compliant with the 2.0A and B (active) specifications with a bit rate of up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive FIFOS with three stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated. Table 13. SAI implementation SAI features(1) 1. X: supported SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X FIFO size X (8 Word) X (8 Word) SPDIF X X PDM X - |
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