TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

18

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Iine control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the

LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates

the need for separate storage of the line characteristics in system memory. The contents of this register are

summarized in Table 3 and are described in the following bulleted list.

These bits are encoded as shown in Table 5.

Table 5. Serial Character Word Length

Bit 1

Bit 0

Word Length

0

0

5 bits

0

1

6 bits

1

0

7 bits

1

1

8 bits

bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated

is dependent on the word length selected with bits 0 and 1. The number of stop bits generated in relation

to word length and bit 2 is as shown in Table 6.

Table 6. Number of Stop Bits Generated

Bit 2

Word Length Selected

Number of Stop

Bit 2

by Bits 1 and 2

Bits Generated

0

Any word length

1

1

5 bits

1 1/2

1

6 bits

2

1

7 bits

2

1

8 bits

2

the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit

3 is cleared, no parity is generated or checked.

(an even number of logic is in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,

odd parity (an odd number of logic 1s) is selected.

cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.

terminal is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled. The

break condition has no affect on the transmitter logic, it only affects the serial output.

baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver

buffer, the THR, or the IER.