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ZL40262 Datasheet(PDF) 17 Page - Microchip Technology |
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ZL40262 Datasheet(HTML) 17 Page - Microchip Technology |
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17 / 36 page ![]() 2024 Microchip Technology Inc. and its subsidiaries. DS20006843A-page 17 ZL40262 TABLE 3-6: POWER SUPPLY REJECTION RATIO FOR VDD = VDDO = 2.5V Note 1, Note 2, Note 3 Parameter Symbol Min Typ. Max Units Condition PSRR for HCSL output PSRRHCSL — –73.5 — dBc fIN = 100 MHz –69.8 fIN = 133 MHz –61.2 fIN = 400 MHz Note 1: Values are over recommended operating conditions. 2: Noise injected to VDD/VDDO power supply with frequency 100 kHz and amplitude 100 mVpp. 3: PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot. TABLE 3-7: HCSL OUTPUTS FOR VDDO = 3.3V Note 1 Parameter Symbol Min Typ. Max Units Condition Rising edge rate rise_rate 1.3 1.7 2 V/ns Note 3, Note 4 Falling edge rate fall_rate 1.3 1.7 2 V/ns Note 3, Note 4 Differential high voltage VIH 0.6 — 0.9 V Note 3 Differential low voltage VIL –0.9 — –0.6 V Note 3 Single ended high voltage VSIH 0.6 0.74 0.85 V DC Measurement Single ended low voltage VSIL –0.01 0 0.01 V DC Measurement Absolute crossing voltage VCROSS 0.26 0.32 0.38 V Note 2, Note 5, Note 6 Variation of VCROSS over all rising clock edges ΔVCROSS 0.039 0.050 0.061 V Note 2, Note 5, Note 10 Ring back voltage margin VRB 0.534 0.674 0.809 V Note 3, Note 12 Time before VRB is allowed tSTABLE 4.6 — — ns Note 3, Note 12 Cycle-to-cycle additive jitter TJCC — 6.5 8.1 ps peak- to-peak Note 3 Absolute maximum voltage VMAX — — 0.92 — Note 2, Note 8 Absolute minimum voltage VMIN –0.05 — — — Note 2, Note 9 Output duty-cycle (when input has 50% duty-cycle) duty_cycle 48 50 52 % Note 3 Rising to falling edge matching r/f match — — 15 % Note 2, Note 13 Clock source DC impedance (CK) ZC-DC_CK 49 50 51 Ω DC Measurement Note 2, Note 14) Clock source DC impedance (CK#) ZC-DC_CK# 49 50 51 Ω DC Measurement Note 2, Note 14 |
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