TUSB1106-Q1

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SCAS916

– AUGUST 2011

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Output enable (CMOS level with respect to VCC(I/O), active LOW). Enables the transceiver to

OE

3

I

transmit data on the USB bus input pad. Push pull, CMOS.

Differential data receiver (CMOS level with respect to VCC(I/O)). Driven LOW when input

RCV

4

O

SUSPND is HIGH. The output state of RCV is preserved and stable during an SE0 condition

output pad. Push pull, 4-mA output drive, CMOS.

Single-ended D+ receiver (CMOS level with respect to V). For external detection of single-ended

VP

5

O

zero (SE0), error conditions, speed of connected device. Driven HIGH when no supply voltage

is connected to VCC(5.0) and Vreg(3.3) output pad. Push pull, 4-mA output drive, CMOS.

Single-ended D

– receiver (CMOS level with respect to VCC(I/O)). For external detection of

single-ended zero (SE0), error conditions, speed of connected device. Driven HIGH when no

VM

6

O

supply voltage is connected to VCC(5.0) and Vreg(3.3) output pad. Push pull, 4-mA output drive,

CMOS.

Suspend (CMOS level with respect to VCC(I/O)). A HIGH level enables low-power state while the

SUSPND

7

I

USB bus is inactive and drives output RCV to a LOW-level input pad. Push pull, CMOS.

Mode (CMOS level with respect to VCC(I/O)). A HIGH level enables the differential input mode

MODE

I

(VPO, VMO), whereas a LOW level enables a single-ended input mode (VO, FSE0). See Table

5 and Table 6 input pad. Push pull, CMOS.

GND

8

Ground supply

Supply voltage for digital I/O pins (1.65 to 3.6 V). When VCC(I/O) is not connected, the D+ and

VCC(I/O)

9

D

– pins are in 3-state. This supply pin is independent of VCC(5.0) and Vreg(3.3) and must never

exceed the Vreg(3.3) voltage.

Speed selection (CMOS level with respect to VCC(I/O)). Adjusts the slew rate of differential data

outputs D+ and D

– according to the transmission speed. Input pad, push pull, CMOS.

SPEED

10

I

LOW

– low speed (1.5 Mbit/s)

HIGH

– full speed (12 Mbit/s)

Negative USB data bus connection (analog, differential). For low-speed mode, connect to pin

D

–

11

AI/O

Vpu(3.3) via a 1.5-kΩ resistor.

Positive USB data bus connection (analog, differential). For full-speed mode, connect to pin

D+

12

AI/O

Vpu(3.3) via a 1.5-kΩ resistor.

VPO/VO

I

Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See Driving Function table.

Push pull, CMOS.

VPO

13

VMO/FSE0

I

Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See Driving Function table.

Push pull, CMOS.

VMO

14

Internal regulator option. Regulated supply-voltage output (3 V to 3.6 V) during 5-V operation. A

decoupling capacitor of at least 0.1 mF is required for the regulator bypass option. Used as a

Vreg(3.3)

15

supply-voltage input for

3.3 V

± 10% operation.

Internal regulator option. Supply-voltage input (4 V to 5.5 V). Can be connected directly to USB

VCC(5.0)

16

supply VBUS regulator bypass option. Connect to Vreg(3.3).

Pullup supply voltage (3.3 V

± 10%). Connect an external 1.5-kΩ resistor on D+ (full speed) or

D

– (low speed). Pin function is controlled by input SOFTCON.

Vpu(3.3)

1

SOFTCON = LOW

– Vpu(3.3) floating (high impedance), ensures zero pullup current

SOFTCON = HIGH

– Vpu(3.3) = 3.3 V, internally connected to Vreg(3.3)

Software-controlled USB connection. A HIGH level applies 3.3 V to pin Vpu(3.3), which is

SOFTCON

2

I

connected to an external 1.5-k

Ω pullup resistor. This allows USB connect/disconnect signaling

to be controlled by software input pad. Push pull, CMOS.

Copyright

© 2011, Texas Instruments Incorporated

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Product Folder Link(s): TUSB1106-Q1