SNP

GND

D1

PIN

GND

PIN

D1

V+

6.5V

D3

ESD

CLAMP

D2

V+

GND

ESD

Clamp

6.5V

D1

D2

D3

160 k

80 k

LM95245

SNIS148G – OCTOBER 2007 – REVISED MARCH 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

Supply Voltage, VDD

−0.3V to 6.0V

Voltage at SMBDAT, SMBCLK, T_CRIT, OS/A0 Pins

−0.5V to 6.0V

Voltage at Other Pins

(VDD +0.3V)

Input Current at D

− Pin (3)

±1 mA

Input Current at All Other Pins

±5 mA

(3)

Output Sink Current, SMBDAT, T_Crit, OS Pins

10 mA

Package Input Current (3)

30 mA

Human Body Model

2500V

ESD Susceptibility (4)

Machine Model

250V

Charged Device Model

1000V

Junction Temperature (5)

+125°C

Storage Temperature

−65°C to +150°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test

conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(2)

Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. Reflow temperature

profiles are different for packages containing lead (Pb) than for those that do not.

(3)

When the input voltage (VI) at any pin exceeds the power supplies (VI < GND or VI > VDD), the current at that pin should be limited to 5

mA. Parasitic components and or ESD protection circuitry are shown in Table 2 for the LM95245's pins. Care should be taken not to

forward bias the parasitic diodes on pins 2 and 3. Doing so by more than 50 mV may corrupt the temperature measurements. SNP

refers to Snap-back device.

(4)

Human body model (HBM) is a charged 100 pF capacitor discharged into a 1.5 k

Ω resistor. Machine model (MM), is a charged 200 pF

capacitor discharged directly into each pin. Charged Device Model (CDM) simulates a pin slowly acquiring charge (such as from a

device sliding down the feeder in an automated assembler) then rapidly being discharged.

(5)

Thermal resistance junction-to-ambient when attached to a printed circuit board with 1 oz. foil and no airflow is:

θJA for VSSOP-8

package = 210°C/W

θJA for SOIC-8 package = 168°C/W

Table 2. ESD Protection

Pin No.

Label

Circuit

Pin ESD Protection Structure Circuits

1

VDD

B

2

D+

A

3

D

−

A

4

T_CRIT

C

Circuit A

Circuit B

5

GND

B

6

OS/A0

C

7

SMBDAT

C

8

SMBCLK

C

Circuit C

4

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