VER.A5 2019.07 Page

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Contents

Features..............................................................................................1

Package..............................................................................................1

Application..........................................................................................1

Functional Description......................................................................1

Typical Application Circuit................................................................1

Pins......................................................................................................2

Internal Block Diagram.....................................................................2

Pin Descriptions................................................................................ 2

Absolute Maximum Ratings.............................................................3

Recommended Operating Conditions........................................... 3

Electrical Characteristics..................................................................3

Typical Curves...................................................................................5

Application Circuit............................................................................. 6

Chip Description................................................................................7

Ordering Information.......................................................................11

Pins

Internal Block Diagram

Pin descriptions

No.

Name

I/O

Description

1

UVP

I

The power supply line input voltage is sensed via a resistor for undervoltage protection

2

FB

I

The voltage feedback pin realizes loop feedback by means of opto-coupler signal and adjusts the PWM

duty cycle ratio in combination with the current sampling (CS) signal.

3

CS

I

Current sampling input pin

4

BOS

I

BOS pin multiplexes: External NTC thermistor for overtemperature protection.

5

RI

I

PWM’s operating frequency set by external resistor to ground which is connected in parallel with a capacitor

for frequency jittering, thus improving full-load EMI.

6

GND

P

Ground reference

7

GATE

O

Power MOSFET gate drive pin

8

VDD

P

Chip power pin