ADC101C027 datasheet(24/46 Pages) TI2

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SCL

SDA

START or

REPEATED

START

STOP

MSB

7-bit Slave Address

R/W

Direction

Bit

Acknowledge

from the Device

MSB

Data Byte

*Acknowledge

or Not-ACK

ACK

N/ACK

Repeated for the Lower Data Byte

and Additional Data Transfers

LSB

*Note: In continuous mode, this bit must be an ACK from

the data receiver. Immediately preceding a STOP

condition, this bit must be a NACK from the master.

ADC101C021, ADC101C027

SNAS446D – FEBRUARY 2008 – REVISED FEBRUARY 2013

www.ti.com

A Repeated Start is generated to address a different device or register, or to switch between read and write

modes. The master generates a Repeated Start condition by driving SDA low while SCL is high. Following the

Repeated Start, the master sends out the slave address and a read/write bit as shown in Figure 22. The bus

continues to operate in the same speed mode as before the Repeated Start condition.

All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop

condition occurs when SDA is pulled high while SCL is high. After a Stop condition, the bus remains idle until a

master generates another Start condition.

Please refer to the Philips I2C® Specification (Version 2.1 Jan, 2000) for a detailed description of the serial

interface.

Figure 22. Basic Operation.

Standard-Fast Mode

In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is

high. The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have

been transmitted by the master, SDA is released by the master and the ADC101C021 either ACKs or NACKs the

address. If the slave address matches, the ADC101C021 ACKs the master. If the address doesn't match, the

ADC101C021 NACKs the master.

For a write operation, the master follows the ACK by sending the 8-bit register address pointer to the ADC. Then

the ADC101C021 ACKs the transfer by driving SDA low. Next, the master sends the upper 8-bits to the

ADC101C021. Then the ADC101C021 ACKs the transfer by driving SDA low. For a single byte transfer, the

master should generate a stop condition at this point. For a 2-byte write operation, the lower 8-bits are sent by

the master. The ADC101C021 then ACKs the transfer, and the master either sends another pair of data bytes,

generates a Repeated Start condition to read or write another register, or generates a Stop condition to end

communication.

A read operation can take place either of two ways:

If the address pointer is pre-set before the read operation, the desired register can be read immediately following

the slave address. In this case, the upper 8-bits of the register, set by the pre-set address pointer, are sent out

by the ADC. For a single byte read operation, the Master sends a NACK to the ADC and generates a Stop

condition to end communication after receiving 8-bits of data. For a 2-byte read operation, the Master continues

the transmission by sending an ACK to the ADC. Then the ADC sends out the lower 8-bits of the ADC register.

At this point, the master either sends an ACK to receive more data or, a NACK followed by a Stop or Repeated

Start. If the master sends an ACK, the ADC sends the next upper data byte, and the read cycle repeats.

If the ADC101C021 address pointer needs to be set, the master needs to write to the device and set the address

pointer before reading from the desired register. This type of read requires a start, the slave address, a write bit,

the address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 27).

Following this sequence, the ADC sends out the upper 8-bits of the register. For a single byte read operation, the

Master must then send a NACK to the ADC and generate a Stop condition to end communication. For a 2-Byte

write operation, the Master sends an ACK to the ADC. Then, the ADC sends out the lower 8-bits of the ADC

Repeated Start. If the master sends an ACK, the ADC sends another pair of data bytes, and the read cycle will

repeat. The number of data words that can be read is unlimited.

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Product Folder Links: ADC101C021 ADC101C027

ADC101C027 Datasheet(PDF) 24 Page - Texas Instruments

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