70

60

50

0

0

1

2

3

4

5

6

80

90

RMS − OutputVoltage − V

OUTPUTCURRENTDISTRIBUTION

vs

OUTPUTVOLTAGE

100

7

40

30

20

10

VCC(H) =15V

VI =1MHz

RL =25 Ω

VCC(L) = ±7.5V

VCC(L) = ±5V

ICC(L)

CurrentDraw

THS6032

www.ti.com....................................................................................................................................................... SLOS233F – APRIL 1999 – REVISED AUGUST 2009

The THS6032 has been specifically designed for ultra low distortion by careful circuit implementation and by

taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended

distortion measurements are shown in Figure 11 through Figure 15. It is commonly known that in the differential

driver configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion

(THD) will be primarily due to the third order harmonics. Additionally, distortion should be reduced as the

feedback resistance drops. This is because the bandwidth of the amplifier increases, which allows the amplifier

to react faster to any nonlinearities in the closed-loop system.

Another significant point is the fact that distortion decreases as the impedance load increases. This is because

the output resistance of the amplifier becomes less significant as compared to the output load resistance.

One problem that has been receiving a lot of attention in the ADSL area is power dissipation. One way to

substantially reduce power dissipation is to lower the power supply voltages. This is because the RMS voltage of

an ADSL central office signal is 1.65-V RMS at each driver's output with a 1:2 transformer. But, to meet ADSL

requirements, the drivers must have a voltage peak-to-RMS crest factor of 5.6 in order to keep the bit-error

probability rate below 10–7. Hence, the power supply voltages must be high enough to accomplish the driver's

peak output voltage of 1.65 V × 5.6 = 9.25 V(PEAK).

This high peak output voltage requirement, coupled with a low RMS voltage requirement, does not lend itself to

conventional high efficiency designs. One way to save power is to decrease the bias currents internal to the

amplifier. The drawback of doing this is an increase in distortion and a lower frequency response bandwidth.

This is where the THS6032 class-G architecture is useful. The class-G output stage utilizes both a high supply

voltage [VCC(H) typically ± 15 V] and a low supply voltage [(VCC(L) typically ± 6 V]. As long as the output voltage is

less than [VCC(L) – 2.5 V], then part of the output current will be drawn from the VCC(L) supplies. If the output

signal goes above this cutoff point [for example, VO > VCC(L) – 2.5 V], then all of the output current will be

supplied by VCC(H).

To ensure that the cutoff point does not introduce distortion into the system, the entire output stage is always

biased on. This constant biasing scheme will cause a decrease in the efficiency over hard switching class-G

circuits, but the very low distortion results tend to outweigh the efficiency loss. The biasing scheme used in the

THS6032 can be shown by the currents being supplied by the VCC(L) power supplies in Figure 37. This graph

shows there is no discrete current transfer point between the VCC(L) supplies and the VCC(H) supplies. This was

done to ensure low distortion throughout the entire output range. By changing the VCC(L) supply voltage, the

system efficiency can be tailored to suit almost any system with high crest factor requirements.

Figure 37.

Copyright © 1999–2009, Texas Instruments Incorporated

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