CDCE706

www.ti.com ........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008

Byte 25, Bits [6:4]: SSC Modulation Amount(1)

SSC2

SSC1

SSC0

Function

Default(2)

0

0

0

SSC modulation amount 0% = SSC bypass for PLL(3)

Yes

0

0

1

SSC modulation amount ±0.1% (center spread)

0

1

0

SSC modulation amount ±0.25% (center spread)

0

1

1

SSC modulation amount ±0.4% (center spread)

1

0

0

SSC modulation amount 1% (down spread)

1

0

1

SSC modulation amount 1.5% (down spread)

1

1

0

SSC modulation amount 2% (down spread)

1

1

1

SSC modulation amount 3% (down spread)

(1)

The PLL must be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by the following

programming sequence: bypass PLL2 (byte 3, bit 6 = 1); write new Modulation Amount (byte 25); re-activate PLL2 (byte 3, bit 6 = 0).

(2)

Unless customer-specific setting

(3)

If SSC bypass is selected, the SSC circuitry of PLL2 is powered down and the SSC output is reset to logic low. The non-SSC output of

PLL2 is not affected by this mode and can still be used.

Byte 25, Bit [7]: Permanently Lock EEPROM Data

EELOCK

Permanently Lock EEPROM (1)

Default(2)

0

No

Yes

1

Yes

(1)

If this bit is set, the actual data in the EEPROM is permanently locked. Note that the EEPROM lock becomes effective when this bit is

set in the EEPROM and not in the internal volatile register. No further programming is possible, even if this bit is set low. Data, however

can still be written via SMBUS to the internal register to change device function on the fly. But new data no longer can be stored into the

EEPROM.

(2)

Unless customer-specific setting

Byte 26, Bits [6:0]: Byte Count(1)

BC6

BC5

BC4

BC3

BC2

BC1

BC0

No. of Bytes

Default(2)

0

0

0

0

0

0

0

Not allowed

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

2

0

0

0

0

0

1

1

3

•

•

•

0

0

1

1

0

1

1

27

Yes

•

•

•

1

1

1

1

1

0

1

125

1

1

1

1

1

1

0

126

1

1

1

1

1

1

1

127

(1)

Defines the number of bytes, which is sent from this device at the next block-read protocol.

(2)

Unless customer-specific setting

Byte 26, Bit [7]: Initiate EEPROM Write Cycle(1)

EEWRITE

Starts EEPROM Write Cycle

Default(2)

0

No

Yes

1

Yes

(1)

The EEPROM WRITE cycle is initiated with the rising edge of the EEWRITE bit. The EEPROM WRITE bit must be sent last to ensure

that the content of all internal registers is stored in the EEPROM. Do not interrupt the EEPROM WRITE cycle; otherwise, random data

can be stored in the EEPROM. A static level-high does not trigger an EEPROM WRITE cycle. This bit stays high until the user resets it

to low (it is not automatically reset after the programming has been completed). Therefore, to initiate an EEPROM WRITE cycle, it is

recommended to send a zero-one sequence to the EEWRITE bit in byte 26.

During EEPROM programming, no data are allowed to be sent to the device via the SMBus until the programming sequence has been

completed. Data, however, can be read out during the programming sequence (byte read or block read). The programming status can

be monitored by reading out EEPIP, byte 24, bit 7. If EELOCK is set, no EEPROM programming is possible.

(2)

Unless customer-specific setting

Copyright © 2005–2008, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Link(s): CDCE706