VCCOUT − Supply Voltage − V

−1

0

1

2

3

4

5

G007

2.5

3

3.6

Multifunction Control Inputs S0 and S1

Output Switching Matrix

CDCE706

SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com

Figure 22. EMI Reduction vs VCCOUT

The CDCE706 features two user-definable input pins which can be used as external control pins or address pins.

When programmed as control pins, they can function as the clock-select pin, enable/disable pin, or device

power-down pin. If both pins are used as address bits, up to four devices can be connected to the same SMBus.

The function is set in byte 10, bits [3:0]. Table 4 shows the possible settings for the different output conditions,

clock select, and device addresses.

Table 4. Configuration Setting of Control Inputs

Configuration Bits

External Control Pins

Device Function

Byte 10,

Byte 10,

Bit [3:2]

Bit [1:0]

S1

S0

Power

S11

S10

S01

S00

Yx Outputs

Pin 2

Pin 1

(Pin 2)

(Pin 1)

Down

0

X

0

X

1

1

Active

No

Output ctrl

Output ctrl

0

0

0

X

0

1

Low/high(1)

No

Output ctrl

Output ctrl

0

1

0

X

0

1

High impedance

Outputs only

Output ctrl

Output ctrl

0

X

0

0

X

0

High impedance

PLL, inputs, and

Output ctrl

Output ctrl and pd

outputs

0

X

0

1

0

0

S10 = 0: low/high(1)

PLL only

Output ctrl

PLL and div. bypass

S10 = 1: high impedance

0

X

0

1

1

0

Active

PLL only

Output ctrl

PLL and div. bypass

0

X

1

0

0

0/1(2)

S10 = 0: Low/High(1)

No

Output ctrl

CLK_SEL

S10 = 1: high impedance

0

X

1

0

1

0/1(2)

Active

No

Output ctrl

CLK_SEL

1

1

1

1

X

X

Active

No

A1(3)

A0(3)

(1)

A noninverting output is set to low, and an inverting output is set to high.

(2)

If S0 is 0, CLK_IN0 is selected; if S0 is 1, CLK_IN1 is selected.

(3)

S0 and S1 are interpreted as address bits A0 and A1 of the slave receiver address byte.

As shown in Table 4, there is a specific order of the different output conditions: power-down mode overwrites

high-impedance state, high-impedance state overwrites low-state, and low-state overwrites active-state.

The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signal

sources via a free-selectable post-divider to any of the six outputs.

As shown in Figure 23, the CDCE706 is based on two banks of switches and six post-dividers. Switch A

comprises six five-input multiplexers which select one of the four PLL clock outputs or directly select the input

clock and feed it to one of the 7-bit post-dividers (P-divider). Switch B is made up of six six-input multiplexers

which take any P-divider and feed it to one of the six outputs, Yx.

28

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