Y0(PLL1), Y1–Y4inHigh-ImpedanceState

MeasuredChannel: Y0

StartCondition:(M=10,N=30)=81MHz

Byte-2Write:N=30(81MHz)>N=110(297MHz)

60 stoPLL Pull-In

·

·

·

·

·

m

f

20 s/div

m

81

297

StartCondition:

Acknowledgeof

N-DividerByte

f

(MHz)

VCO

Frequency

Response

Curveof Y0

0

60

t( s)

m

C005

Power-Supply Sequencing

Device Behavior During Supply-Voltage Drops

CDCE706

SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com

Figure 33. Snapshot of the PLL Lock-Time

The CDCE706 includes three power-supply pins, VCC, VCCOUT1, and VCCOUT2. There are no power-supply

sequencing requirements, as the three power nodes are separated from each other. So, power can be supplied

in any order to the three nodes.

Also, the part has power-up circuitry which switches the device on if VCC exceeds 2.1 V (typ) and switches the

device off at VCC < 1.7 V (typ). In power-down mode, all outputs and clock inputs are switched off.

The CDCE706 has a power-up circuit, which activates the device functionality at VPUC_ON (typical 2.1 V). At the

same time, the EEPROM information is loaded into the register. This mechanism ensures that there is a

predefined default after power up and no need to reprogram the CDCE706 in the application.

In the event of a supply-voltage drop, the power-up circuit ensures that there is always a defined setup within the

register. Figure 34 shows possible voltage drops with different amplitudes.

36

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