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DLP2000 Datasheet(PDF) 26 Page - Texas Instruments

Part # DLP2000
Description  DLP2000 (.2 nHD) DMD
PDF  37 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DLP2000 Datasheet(HTML) 26 Page - Texas Instruments

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Mirror Park Sequence
VSS
DMD_PWR_EN
Power Off
VBIAS, VOFFSET, and VRESET are disabled by DLP Display Controller software
VRESET
VRESET
VSS
VRESET
VOFFSET
VSS
VOFFSET
VOFFSET
Note 5
ûV < Specification
VOFFSET < Specification
VBIAS
VBIAS
VSS
VSS
VBIAS
VBIAS < Specification
VSS
VSS
VCC
VSS
VCC
VCC
VSS
LVCMOS
Inputs
VSS
Note 6
Note 6
Note 6
Note 2
VSS
Note 3
Note 4
VCC
VSS
Note 1
VRESET > Specification
VRESET < Specification
ûV < Specification
Note 5
VCC
Refer to specifications listed in section Recommended Operating Conditions.
Waveforms are not to scale. Details are omitted for clarity.
Figure 9-1. DMD Power Supply Sequencing Requirements
Note 1: Refer to specifications listed in Section 6.4 . Waveforms are not to scale. Details are omitted for clarity.
Note 2: DMD_PWR_EN is not a package pin on the DMD. It is a signal from the DLP Display Controller
(DLPC2607) that enables the VRESET, VBIAS, and VOFFSET regulators on the system board.
Note 3: After the DMD micromirror park sequence is complete, the DLP display controller (DLPC2607) software
initiates a hardware power-down that disables VBIAS, VRESET and VOFFSET.
Note 4: During the micromirror parking process, VCC, VBIAS, VOFFSET, and VRESET power supplies are all required
to be within the specification limits in Section 6.4 . Once the micromirrors are parked, VBIAS, VOFFSET, and
VRESET power supplies can be turned off.
Note 5: To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in
Section 6.4 . It is critical to meet this requirement and that VBIAS not reach full power level until after VOFFSET is at
almost full power level. OEMs may find that the most reliable way to ensure this is to delay powering VBIAS until
after VOFFSET is fully powered on during power-up (and to remove VBIAS prior to VOFFSET during power down). In
this case, VOFFSET is run at its maximum allowable voltage level (8.75 V).
Note 6: Refer to specifications listed in Table 9-1.
DLP2000
DLPS140B – MARCH 2019 – REVISED MAY 2022
www.ti.com
26
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