PWM

OUT

GND

LM5032

VCC

LM5032

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SNVS344B – MARCH 2005 – REVISED DECEMBER 2014

Feature Description (continued)

Line Voltage Maximum Duty Cycle. The voltage at the UVLO pin, normally proportional to the voltage at VPWR,

further limits the maximum duty cycle at high input voltages. Referring to Figure 10, when the UVLO pin is below

1.25V, the outputs are disabled. At UVLO = 1.25V the maximum allowed duty cycle is 80% (or less if limited by

the DCL resistor). As the UVLO pin voltage increases with VPWR, the maximum duty cycle decreases, reaching a

minimum of 10% at

≊4.5V. Referring to the UVLO voltage, after passing through an inverting gain stage, is

compared to the Ramp1 and Ramp2 signals generated by the oscillator. The output of these comparators are the

MaxDC1 and MaxDC2 timing signals. These signals are provided to the two 4-input AND gates which limit the

PWM pulses delivered to the output drivers.

Resulting Output Duty Cycle. The controller duty cycle is determined by the four signals into the 4-input AND

gates in (UserMaxDC, MaxDC, PWM and CLK). The output driver pulsewidth is equal to the least of these four

pulses. Whichever input of the AND gate transitions high-to-low first terminates the output driver’s on-time.

7.3.10 Driver Outputs

OUT1, the primary switch driver for Controller 1 is designed to drive the gate of an N-channel MOSFET with 1.5A

sourcing current and 2.5A sinking current. The peak output levels are VCC and GND1. The ground return path

for Controller 1 is GND1. The corresponding pins for Controller 2 are OUT2 and GND2.

OUT1 and OUT2 are compound gate drivers with CMOS and Bipolar output transistors as shown in Figure 18.

The parallel MOS and Bipolar devices provide a faster turn-off of the primary switch thereby reducing switching

losses. The outputs switch at one-half the oscillator frequency with the rising edges at OUT1 and OUT2 180° out

of phase with each other. The on-time of OUT1 and OUT2 is determined by their respective duty cycle control.

Figure 18. Compound Gate Driver

7.3.11 Thermal Shutdown

The LM5032 should be operated so the junction temperature does not exceed 125°C. If a junction temperature

transient reaches 165°C (typical), the Thermal Shutdown circuit activates the VCC Disable and Drivers Off lines

(see Figure 14). The VCC regulator and the four output drivers are disabled, the SS1, SS2, and RES pins are

grounded, and the soft-start current is set to 50 µA. This puts the LM5032 in a low power state helping to prevent

catastrophic failures from accidental device overheating. When the junction temperature reduces below 145°C

(typical hysteresis = 20°C), the VCC regulator is enabled and a startup sequence is initiated (Figure 1).

7.4 Device Functional Modes

Normal device operating mode is described above in sections Line Undervoltage Lock Out, UVLO, Shutdown

through Cycle-by-Cycle Current Limit, and sections Soft-Start to Thermal Shutdown. Under overcurrent fault

conditions, the device operate in Hiccup Mode, as detailed above in the Hiccup Mode Current Limit Restart

section.

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