AD6653-125EBZ datasheet(53/80 Pages) AD

53 / 80 page

AD6653

Rev. 0 | Page 53 of 80

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system-level design and layout of the AD6653,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD6653, it is recommended

that two separate 1.8 V supplies be used: one supply should be

used for analog (AVDD) and digital (DVDD), and a separate

supply should be used for the digital outputs (DRVDD). The

AVDD and DVDD supplies, while derived from the same source,

should be isolated with a ferrite bead or filter choke and separate

decoupling capacitors. The designer can employ several different

decoupling capacitors to cover both high and low frequencies.

These capacitors should be located close to the point of entry

at the PC board level and close to the pins of the part with

minimal trace length.

A single PCB ground plane should be sufficient when using the

AD6653. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

fS/2 Spurious

Because the AD6653 output data rate is at one-half the sampling

frequency, there is significant fS/2 energy in the outputs of the

part. If this fS/2 spur falls in band, care must be taken to ensure

that this fS/2 energy does not couple into either the clock circuit

or the analog inputs of the AD6653. When fS/2 energy is coupled

in this fashion, it appears as a spurious tone reflected around fS/4,

3fS/4, 5fS/4, and so on. For example, in a 125 MSPS sampling

application with a 90 MHz single-tone analog input, this energy

generates a tone at 97.5 MHz. In this example, the center of the

Nyquist zone is 93.75 MHz; therefore, the 90 MHz input signal is

3.75 MHz from the center of the Nyquist zone. As a result, the fS/2

spurious tone appears at 97.5 MHz, or 3.75 MHz above the center

of the Nyquist zone. These frequencies are then tuned by the NCOs

before being output by the AD6653.

Depending on the relationship of the IF frequency to the center

of the Nyquist zone, this spurious tone may or may not exist in the

AD6653 output band. Some residual fS/2 energy is present in

the AD6653, and the level of this spur is typically below the

level of the harmonics at clock rates of 125 MSPS and below.

Figure 80 shows a plot of the fS/2 spur level vs. analog input

frequency for the AD6653-125. At sampling rates above

125 MSPS, the fS/2 spur level increases and is at a higher level

than the worst harmonic as shown in Figure 81, which shows

the AD6653-150 fS/2 levels.

For the specifications provided in Table 2, the fS/2 spur, if in

band, is excluded from the SNR values. It is treated as a

harmonic, in terms of SNR. The fS/2 level is included in the

SFDR and worst other specifications.

–60

–70

–80

–90

–100

–110

–120

100

150

200

250

350

300

400

450

500

INPUT FREQUENCY (MHz)

fS/2 SPUR

–SFDR

Figure 80. AD6653-125 SFDR and fS/2 Spurious Level vs. Input Frequency (fIN)

with DRVDD = 1.8 V Parallel CMOS Output Mode

–60

–70

–80

–90

–100

–110

–120

100

150

200

250

350

300

400

450

500

INPUT FREQUENCY (MHz)

–SFDR

fS/2 SPUR

Figure 81. AD6653-150 SFDR and fS/2 Spurious Level vs. Input Frequency (fIN)

with DRVDD = 1.8 V Parallel CMOS Output Mode

Operating the part with a 1.8 V DRVDD voltage rather than 3.3 V

DRVDD lowers the fS/2 spur. In addition, using LVDS, CMOS

interleaved, or CMOS IQ output modes also reduces the fS/2

spurious level.

LVDS Operation

The AD6653 defaults to CMOS output mode on power-up.

If LVDS operation is desired, this mode must be programmed

using the SPI configuration registers after power-up. When the

AD6653 powers up in CMOS mode with LVDS termination

resistors (100 Ω) on the outputs, the DRVDD current can be

higher than the typical value until the part is placed in LVDS

mode. This additional DRVDD current does not cause damage

to the AD6653, but it should be taken into account when consid-

ering the maximum DRVDD current for the part.

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