DAC7678SPW datasheet(35/57 Pages) TI2

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DAC7678

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SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014

POWER-ON RESET TO ZERO-SCALE OR

Alternatively, all DAC outputs can be updated

MID-SCALE

simultaneously using the built-in LDAC software

function. The LDAC register offers additional flexibility

The DAC7678 contains a power-on reset (POR)

and control, giving the ability to select which DAC

circuit that controls the output voltage during power-

channel(s) should be updated simultaneously when

on. For devices housed in the TSSOP package, at

the hardware LDAC pin is being brought low. The

power-on, all DAC registers are filled with zeros and

LDAC register is loaded with an 8-bit word (DB15 to

the output voltages of all DAC channels are set to

DB8) using control bits C3, C2, C1, and C0. The

zero-scale. For devices housed in the QFN package,

default value for each bit, and therefore each DAC

all DAC registers are set to have all DAC channels

channel, is zero and the external LDAC pin operates

power on depending of the state of the RSTSEL pin.

in normal mode. If the LDAC register bit for a

selected DAC channel is set to '1', that DAC channel

The RSTSEL pin value is read at power-on and

ignores the external LDAC pin and updates only

should be set prior to or simultaneously with AVDD.

through the software LDAC command. If, however,

For RSTSEL set to AVDD, the DAC channels are

the LDAC register bit is set to '0', the DAC channel is

loaded with midscale code. If RSTSEL is set to

controlled by the external LDAC pin.

ground, the DAC channels are loaded with zero-scale

code. All DAC channels remain in this state until a

This

combination

software

and

hardware

valid write sequence and load command are sent to

simultaneous update function is particularly useful in

the respective DAC channel. The power-on reset

applications where only selective DAC channels are

function is useful in applications where it is important

to be updated simultaneously, while keeping the other

to know the output state of each DAC while the

channels unaffected and updating those channels

device is in the process of powering on.

synchronously.

The internal reference is powered off/down by default,

and remains that way until a valid reference-change

POWER-DOWN MODES

command is executed.

The DAC7678 has two separate sets of power-down

commands. One set is for the DAC channels and the

LDAC FUNCTIONALITY

other set is for the internal reference. For more

information on powering down the reference see the

The DAC7678 offers both software and hardware

Enable/Disable Internal Reference section.

simultaneous updates and control functions. The

DAC double-buffered architecture is designed so that

DAC Power-Down Commands

new data can be entered for each DAC without

disturbing the analog outputs.

The DAC7678 uses four modes of operation. These

modes are accessed by using control bits C3, C2,

The DAC7678 data updates can be performed either

C1, and C0. The control bits must be set to '0100'.

in synchronous or asynchronous mode.

When the control bits are set correctly, the four

In synchronous mode, data are updated on the falling

different

power-down

modes

are

software

edge of the acknowledge signal that follows LSDB.

programmable by setting bits PD0 (DB13) and PD1

For synchronous mode updates, the LDAC pin is not

(DB14) in the control register. Table 19 shows how to

required

and

must

connected

GND

control the operating mode with data bits PD0 (DB13)

permanently.

and PD1 (DB14). The DAC7678 treats the power-

down condition as data; all the operational modes are

In asynchronous mode, the LDAC pin is used as a

still valid for power down. It is possible to broadcast a

negative-edge-triggered

timing

signal

for

power-down condition to all the DAC7678s in a

asynchronous DAC updates. Multiple single-channel

system. It is also possible to power-down a channel

updates can be performed in order to set different

and update data on other channels. Furthermore, it is

channel buffers to desired values and then make a

possible to write to the DAC register/buffer of the

falling edge on the LDAC pin. The data buffers of all

DAC channel that is powered down. When the DAC

the channels must be loaded with the desired data

channel is then powered on, it will contain this new

before an LDAC falling edge. After a high-to-low

value.

LDAC

transition,

all

DACs

are

simultaneously

updated with the last contents of the corresponding

data buffers. If the contents of a data buffer are not

changed by the serial interface, the corresponding

DAC output remains unchanged after the LDAC

trigger.

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