DAC8750IPWPR datasheet(21/56 Pages) TI2

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For a 5-V reference, the output can be expressed as shown in Equation 1 through Equation 3.

For a 0-mA to 20-mA output range, use Equation 1.

CODE

IOUT

20mA •

(1)

For a 0-mA to 24-mA output range, use Equation 2.

CODE

IOUT

24mA •

(2)

For a 4-mA to 20-mA output range, use Equation 3.

CODE

IOUT

16mA •

4mA

(3)

where

• CODE is the decimal equivalent of the code loaded to the DAC

• N is the bits of resolution; 16 for DAC8750, and 12 for DAC7750

The current-output range is normally set according to the value of the RANGE bits in the Control Register (see

Section 8.4.1 for more details).

8.3.3 Internal Reference

The DACx750 includes an integrated 5-V reference with a buffered output (REFOUT) capable of driving up

to 5 mA (source or sink) with an initial accuracy of ±5 mV maximum and a temperature drift coefficient of 10

ppm/°C maximum.

8.3.4 Digital Power Supply

An internally generated 4.6-V supply capable of driving up to 10 mA can be output on DVDD by leaving the

DVDD-EN pin unconnected. This configuration simplifies the system power-supply design when an isolation

barrier is required to generate the digital supply. The internally generated supply can be used to drive isolation

components used for the digital data lines and other miscellaneous components, such as references and

temperature sensors; see Figure 9-3 for an example application.

If an external supply is preferred, the DVDD pin (which can be driven up to 5.5 V in this case) can become an

input by tying DVDD-EN to GND. See Section 7.5 for detailed specifications.

8.3.5 DAC Clear

The DAC has an asynchronous clear function through the CLR pin that is active-high and allows the current

output to be cleared to zero-scale code. When the CLR signal returns to low, the output remains at the cleared

value. The preclear value can be restored by pulsing the LATCH signal without clocking any data. A new value

cannot be programmed until the CLR pin returns to low. To avoid glitches on the output, disable the output by

writing a 0 to the OUTEN bit of the Control Register before changing the current range.

8.3.6 Power-On Reset

The DACx750 incorporates two internal POR circuits for the DVDD and AVDD supplies. The DVDD and AVDD

POR signals are ANDed together so that both supplies must be at their minimal specified values for the device

to not be in a reset condition. These POR circuits initialize internal logic and registers, as well as set the analog

outputs to a known state while the device supplies are ramping. All registers are reset to their default values.

Typically the POR function can be ignored, as long as the device supplies power-up and maintains the specified

minimum voltage levels. However, in the case of a supply drop or brownout, the DACx750 can have an internal

POR reset event or lose digital memory integrity. Figure 8-3 represents the threshold levels for the internal POR

for both the DVDD and AVDD supplies.

www.ti.com

DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

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