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L9800 Datasheet(PDF) 44 Page - STMicroelectronics |
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L9800 Datasheet(HTML) 44 Page - STMicroelectronics |
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44 / 55 page ![]() Table 18. Register addressing space Field name Type Bit offset Bit width Reset value Reset source Description CHIP_ID, 0x00 CHIP_ID RO 0 8 00100010 X 8-bit chip identifier CFG_0, 0x01 NU RO 6 2 0x00 X Not used NRES_N_EN RW 5 1 NPOR, CFG_1.RST, VDD_UV 0 (default): NRES pin masked 1: NRES pin NOT masked (not cleared after an NRES reset) ACTIVE TO SLEEP DIS SWR RW 4 1 0x00 NPOR, NRES pin, CFG_1.RST, VDD_UV 0 (default): SW reset required for transition ACTIVE to SLEEP 1: SW reset NOT required for transition ACTIVE to SLEEP RESERVED RW 3 1 0x00 NPOR, NRES pin, CFG_1.RST, VDD_UV Reserved VS_UV_MASK RW 2 1 0x00 NPOR, NRES pin, CFG_1.RST, VDD_UV 0 (default): VBATT UV not masked 1: VBATT UV masked but STA_1 diag bit still working DIS_EN RW 1 1 0x00 NPOR, NRES pin, CFG_1.RST bit, VDD_UV 0: (default) DIS pin masked 1: DIS pin not masked NRES_EN RW 0 1 0x00 NPOR, NRES pin, CFG_1.RST bit, VDD_UV 0 (default): NRES pin masked 1: NRES pin not masked CFG_1, 0x02 RST WO 7 1 0x00 NPOR, NRES pin, CFG_1.RST bit, VDD_UV Reset: 0: (default) normal operation 1: Execute reset command (self-clearing) ACT RW 6 1 0x00 NPOR, NRES pin, CFG_1.RST bit, VDD_UV Active mode: 0: (default) normal operation or device leaves active mode 1: device enters active mode NU RO 2 4 0x00 X PWM_DIV_LED RW 0 2 0x00 NPOR, NRES pin, CFG_1.RST bit, VDD_UV Clock division factor for PWM LED generator PWM frequency: 00 (default): PWM_FRQ = 122 Hz 01: PWM_FRQ = 244 Hz 10: PWM_FRQ = 488 Hz 11: PWM_FRQ = 976 Hz CFG_2, 0x03 NU RO 6 2 0x00 X RESERVED RW 4 2 0x00 NPOR, NRES pin, CFG_1.RST bit, VDD_UV Reserved FR_ADJ RW 2 2 0x00 NPOR, NRES pin, CFG_1.RST bit, VDD_UV PWM generator and LED frequency adjustment bit (15% of selected frequency): 00: no frequency adjustment 01: -15% on selected frequency 10: +15% on selected frequency 11: no frequency adjustment L9800 Serial peripheral interface (SPI) DS14041 - Rev 2 page 44/55 |
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