STA333BW datasheet(16/68 Pages) STMICROELECTRONICS

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Serial audio interface

STA333BW

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DocID13773 Rev 5

Serial audio interface

The STA333BW audio serial input interface was designed to interface with standard digital

audio components and to accept a number of serial data formats. The STA333BW always

acts as the slave when receiving audio input from standard digital audio components. Serial

data for two channels is provided using three inputs: left/right clock LRCKI, serial clock

BICKI, and serial data SDI12.

The SAI bit and the SAIFB bit are used to specify the serial data format. The default serial

data format is I²S, MSB-first.

4.0.1

Timings

In the STA333BW the BICKI and LRCKI pins are configured as inputs and they must be

supplied by the external peripheral.

Figure 6. Timing diagram for SAI interface

4.0.2

Delay serial clock enable

To tolerate anomalies in some I²S master devices, a PLL clock cycle delay can be added to

the BICKI signal before the SAI interface.

4.0.3

Channel input mapping

Each channel received via I²S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I²S input channel to its corresponding processing channel.

Table 8. Timing parameters for slave mode

Symbol

Parameter

Min

Typ

Max

Unit

tBCy

BICK cycle time

tBCH

BICK pulse width high

tBCL

BICK pulse width low

tLRSU

LRCKI setup time to BICKI strobing edge

tLRH

LRCKI hold time to BICKI strobing edge

tLRJT

LRCKI Jitter Tolerance

tBCy

tLRH

tLRSU

LRCKI

BICKI

SDI12

tBCH

tBCL

80%

40%

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