STA333BW datasheet(27/68 Pages) STMICROELECTRONICS

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STA333BW

To make the STA333BW work properly, the serial audio interface LRCKI clock must be

synchronous to the PLL output clock. It means that:

 N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,

where N depends on the settings in Table 13 on page 24

 the PLL must be locked.

If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the

STA333BW immediately mutes the I²S PCM data out (provided to the processing block) and

it freezes any active processing task.

Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI

SAI [3:0]

SAIFB

Interface Format

32 * fs

1100

I²S 15-bit data

1110

Left/right-justified 16-bit data

48 * fs

0100

I²S 23-bit data

0100

I²S 20-bit data

1000

I²S 18-bit data

1100

LSB first I²S 16-bit data

0001

Left-justified 24-bit data

0101

Left-justified 20-bit data

1001

Left-justified 18-bit data

1101

Left-justified 16-bit data

0010

Right-justified 24-bit data

0110

Right-justified 20-bit data

1010

Right-justified 18-bit data

1110

Right-justified 16-bit data

64 * fs

0000

I²S 24-bit data

0100

I²S 20-bit data

1000

I²S 18-bit data

1100

LSB first I²S 16-bit data

0001

Left-justified 24-bit data

0101

Left-justified 20-bit data

1001

Left-justified 18-bit data

1101

Left-justified 16-bit data

0010

Right-justified 24-bit data

0110

Right-justified 20-bit data

1010

Right-justified 18-bit data

1110

Right-justified 16-bit data

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