STA333BW datasheet(28/68 Pages) STMICROELECTRONICS

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STA333BW

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DocID13773 Rev 5

Clock desynchronization can happen during STA333BW operation because of source

switching or TV channel change. To avoid audio side effects, like click or pop noise, it is

strongly recommended to complete the following actions:

soft volume change

I²C read / write instructions

while the serial audio interface and the internal PLL are still synchronous.

Delay serial clock enable

Channel input mapping

Each channel received via I²S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default

settings of these registers maps each I²S input channel to its corresponding processing

channel.

7.1.3

Configuration register C (addr 0x02)

FFX power output mode

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

Table 21. Delay serial clock enable

Bit

R/W

RST

Name

Description

R/W

DSCKE

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I²S master devices

Table 22. Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

C1IM

0: processing channel 1 receives left I²S Input

1: processing channel 1 receives right I²S Input

7R/W

C2IM

0: processing channel 2 receives left I²S Input

1: processing channel 2 receives right I²S Input

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

Table 23. FFX power output mode

Bit

R/W

RST

Name

Description

R/W

OM0

Selects configuration of FFX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

1R/W

OM1

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