DRV8801PWPR datasheet(4/39 Pages) TI2

4 / 39 page

Table 5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

DRV8800

DRV8801

WQFN

HTSSOP

WQFN

HTSSOP

ENABLE

Enable logic input. Set high to enable the H-

bridge.

GND

2,12

4, 13

2, 12

4, 13

Device ground

MODE

—

Mode logic input

MODE 1

—

Mode logic input

MODE 2

—

Mode 2 logic input

—

No connect

nFAULT

Fault indication. Pulled logic low with fault

condition; open-drain output requires an external

pullup resistor.

nSLEEP

Sleep mode input. Logic high to enable device;

logic low to enter low-power sleep mode; internal

pulldown resistor.

OUT+

DMOS H-bridge output. Connect to motor

terminal.

OUT-

DMOS H-bridge output. Connect to motor

terminal.

PHASE

WQFN Package: Phase logic input for direction

control.

HTSSOP Package: Phase logic input. Controls

the direction of the H-bridge.

SENSE

O (DRV8800)

IO (DRV8801)

Sense Power Return

VBB

Driver supply voltage. Bypass to GND with 0.1-μF

ceramic capacitors plus a bulk capacitor rated for

VBB.

VCP

Charge pump reservoir capacitor pin. Connect a

X7R, 0.1-μF, 16-V ceramic capacitor to VBB.

VREG

—

Regulated voltage.

VPROPI

—

Voltage output proportional to winding current.

PowerPAD

—

Exposed pad for thermal dissipation. Connect to

ground.

DRV8800, DRV8801

SLVS855K – JULY 2008 – REVISED MARCH 2021

www.ti.com

Submit Document Feedback

Product Folder Links: DRV8800 DRV8801

DRV8801PWPR Datasheet(PDF) 4 Page - Texas Instruments

DRV8801PWPR Datasheet(HTML) 4 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Datasheet Download

Link URL