L9305EP datasheet(46/107 Pages) STMICROELECTRONICS

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Table 34. Core thermal monitoring electrical performance

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

CORE_ot

CORE over temperature shut down threshold

175

–

185

°C

CORE_ot_hyst

CORE over temperature hysteresis

–

°C

CORE_ot_filt

Digital deglitch

Guaranteed by scan

µs

8.6

IC data verification

All read/write registers are mirrored thus resulting in a main register and a mirror register. The contents of each

and its mirror register occur, an associated fault bit is set as described below :

•

A global register mismatch flag (SERVFLT1, D[2]) is associated to the global registers

–

SERVENA

–

SOLENDR

–

TIMEOUTSPICFG

–

FSCONF

–

SERVFLTMSK1

–

SERVFLTMSK2

•

A channel register mismatch flag (EXCEPTIONS2, D[0]) is dedicated to each channel register bank

–

CONFIGURATION1

–

CONFIGURATION2

–

DITHPGM1

–

DITHPGM2

–

SETPOINT

–

CTRLCFG

–

KFREQCTRL

–

KGAINS

–

INTGLIM

–

DRVFLTMASK1

–

DRVFLTMASK2

–

BASEHLDELTACURR

All the flags are cleared-on-read and refer to the entire register bank. No action is taken when a mismatch arises.

Data mismatch flags can also be mapped to FAULTn pin using SERVFLTMSK1, D[2] for global register and

DRVFLTMSK2, D[0] for channel registers. These flags are masked by default and must be enabled by the users

as per their system needs.

L9305

Safety features

DS12774 - Rev 10

page 46/107

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