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L9305EP Datasheet(PDF) 69 Page - STMicroelectronics |
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L9305EP Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 107 page  SERVFLTMSK2 Service fault mask 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RW R RW R RW RW RW RW RW Address: Fault Test Base Address + 0x06 Type: RW Reset: 0xFFFF Description: Service Fault Mask register allows the user to map specific fault flags to the FAULTn pin. Setting mask bit high disables (masks) fault from setting FAULTn pin. [15] Unused [14] Clamp Inhibit Monitor 0: Mask Disabled 1: Mask Enabled [13:8] Unused [7] SPI Protocol Error 0: Mask Disabled 1: Mask Enabled [6:5] Unused [4] IN3 0: Mask Disabled 1: Mask Enabled [3] IN2 0: Mask Disabled 1: Mask Enabled [2] IN1 0: Mask Disabled 1: Mask Enabled [1] IN0 0: Mask Disabled 1: Mask Enabled [0] EN_DR 0: Mask Disabled 1: Mask Enabled L9305 SPI DS12774 - Rev 10 page 69/107 |
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