SC16C852LIB datasheet(63/63 Pages) NXP

63 / 63 page

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 January 2008

Document identifier: SC16C852L_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 5

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional description . . . . . . . . . . . . . . . . . . 11

6.1

UART A-B functions . . . . . . . . . . . . . . . . . . . . 12

6.2

Extended mode (128-byte FIFO) . . . . . . . . . . 12

6.3

Internal registers . . . . . . . . . . . . . . . . . . . . . . . 13

6.4

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4.1

32-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . 14

6.4.2

128-byte FIFO mode. . . . . . . . . . . . . . . . . . . . 14

6.5

Hardware ﬂow control . . . . . . . . . . . . . . . . . . . 14

6.6

Software ﬂow control . . . . . . . . . . . . . . . . . . . 15

6.7

Special character detect . . . . . . . . . . . . . . . . . 16

6.8

Interrupt priority and time-out interrupts . . . . . 16

6.9

Programmable baud rate generator . . . . . . . . 17

6.10

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 19

6.11

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 19

6.12

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.12.1

Conditions to enter Sleep mode . . . . . . . . . . . 21

6.12.2

Conditions to resume normal operation . . . . . 21

6.13

Low power feature . . . . . . . . . . . . . . . . . . . . . 21

6.14

RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 22

6.14.1

Auto RS-485 RTS control . . . . . . . . . . . . . . . . 22

6.14.2

RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 22

6.14.3

Auto 9-bit mode (RS-485) . . . . . . . . . . . . . . . . 22

6.14.3.1

Normal Multi-drop mode . . . . . . . . . . . . . . . . . 22

6.14.3.2

Auto address detection . . . . . . . . . . . . . . . . . . 23

7.1

Transmit (THR) and Receive (RHR) Holding

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2

Interrupt Enable Register (IER) . . . . . . . . . . . 26

7.2.1

IER versus Transmit/Receive FIFO interrupt

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 27

7.2.2

IER versus Receive/Transmit FIFO polled

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 27

7.3

FIFO Control Register (FCR) . . . . . . . . . . . . . 28

7.3.1

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3.1.1

Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 28

7.3.1.2

Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 28

7.3.2

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.4

Interrupt Status Register (ISR) . . . . . . . . . . . . 30

7.5

Line Control Register (LCR) . . . . . . . . . . . . . . 31

7.6

Modem Control Register (MCR) . . . . . . . . . . . 32

7.7

Line Status Register (LSR) . . . . . . . . . . . . . . 33

7.8

Modem Status Register (MSR) . . . . . . . . . . . 34

7.9

Extra Feature Control Register (EFCR) . . . . . 35

7.10

Scratchpad Register (SPR) . . . . . . . . . . . . . . 35

7.11

Division Latch (DLL and DLM) . . . . . . . . . . . . 35

7.12

Transmit FIFO Level Count (TXLVLCNT) . . . . 35

7.13

Receive FIFO Level Count (RXLVLCNT) . . . . 35

7.14

Enhanced Feature Register (EFR). . . . . . . . . 36

7.15

Transmit Interrupt Level register (TXINTLVL) . 37

7.16

Receive Interrupt Level register (RXINTLVL) . 37

7.17

Flow Control Trigger Level High (FLWCNTH). 38

7.18

Flow Control Trigger Level Low (FLWCNTL) . 38

7.19

Clock Prescaler (CLKPRES) . . . . . . . . . . . . . 38

7.20

RS-485 turn-around time delay (RS485TIME) 39

7.21

Advanced Feature Control Register 2

(AFCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.22

Advanced Feature Control Register 1

(AFCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.23

SC16C852L external reset condition and

software reset. . . . . . . . . . . . . . . . . . . . . . . . . 41

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42

Static characteristics . . . . . . . . . . . . . . . . . . . 42

Dynamic characteristics . . . . . . . . . . . . . . . . . 43

10.1

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 45

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 55

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.1

Introduction to soldering. . . . . . . . . . . . . . . . . 58

12.2

Wave and reﬂow soldering . . . . . . . . . . . . . . . 58

12.3

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 58

12.4

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 59

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 60

Revision history . . . . . . . . . . . . . . . . . . . . . . . 61

Legal information . . . . . . . . . . . . . . . . . . . . . . 62

15.1

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 62

15.2

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

15.3

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 62

15.4

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Contact information . . . . . . . . . . . . . . . . . . . . 62

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

SC16C852LIB Datasheet(PDF) 63 Page - NXP Semiconductors

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