L9942 datasheet(29/40 Pages) STMICROELECTRONICS

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L9942

Logic with SPI - electrical characteristics

Doc ID 11778 Rev 7

29/40

6.3

Outputs: DO, PWM

6.4

Output: DO timing

6.5

CSN timing

Table 23.

Outputs: DO, PWM

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDOoutL

Output low level

VCC = 5 V, ID = 2 mA

0.2

0.4

VPWMoutL

VDOoutH

output high level

VCC = 5 V, ID = -2 mA

VCC -

0.4

VCC -

0.2

-V

VPWMoutH

IDOoutLK

Tristate leakage current

VCSN = VCC,

0 V < VDO< VCC

-10

µA

IPWMoutLK Tristate leakage current

Register3bit5=1 (NPWM)

0 V < VPWM < VCC

-10

µA

Cout

(1)

Tristate input capacitance

VCSN = VCC,

0 V < VCC < 5.3 V

Table 24.

Output: DO timing (see Figure 12 and Figure 13)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tr DO

DO rise time

CL = 100 pF, Iload = -1 mA

100

tf DO

DO fall time

CL = 100 pF, Iload = 1 mA

100

ten DO tri L

DO enable time from tristate to low

level

CL = 100 pF, Iload = 1 mA pull-

up load to VCC

250

tdis DO L tri

DO disable time from low level to

tristate

CL = 100 pF, Iload = 4 mA pull-

up load to VCC

250

ten DO tri H

DO enable time from tristate to

high level

CL = 100 pF, Iload = -1 mA pull-

down load to GND

250

tdis DO H tri

DO disable time from high level to

tristate

CL = 100 pF, Iload = -4 mA

pull-down load to GND

250

td DO

DO delay time

VDO < 0.3 VCC, VDO > 0.7

VCC, CL = 100 pF

250

Table 25.

CSN timing

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tCSN_HI,min

(1)

CSN high time, active mode

Transfer of SPI-command to

Input Register

µs

Parameter guaranteed by design.

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