INA210 datasheet(35/50 Pages) TI2

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Table 7-36. Mask/Enable Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

CVRF

R/W

Conversion-ready flag. Although the INA3221 can be read at any time, and the data

from the last conversion are available, the conversion ready bit is provided to help

coordinate single-shot conversions. The conversion bit is set after all conversions are

complete. Conversion ready clears under the following conditions:

Writing the Configuration register (except for power-down or disable-mode

selections).

Reading the Mask/Enable register.

7.6.2.17 Power-valid Upper-limit Register (address = 10h) [reset = 2710h]

This register contains the value used to determine if the power-valid conditions are met. The power-valid

condition is reached when all bus-voltage channels exceed the value set in this limit register. When the power-

valid condition is met, the PV alert pin asserts high to indicate that the INA3221 has confirmed all bus voltage

channels are above the power-valid upper-limit value. For the power-valid conditions to be monitored, the bus

measurements must be enabled through one of the corresponding MODE bits set in the Configuration register.

The power-valid upper-limit LSB value is 8mV. Power-on reset value is 2710h = 10.000V.

Table 7-37. Power-Valid Upper-Limit Register

SIGN

PVU11 PVU10 PVU9

PVU8

PVU7

PVU6

PVU5

PVU4

PVU3

PVU2

PVU1

PVU0

—

R-0

RW-0

RW-1

RW-0

RW-1

RW-0

RW-1

RW-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7-38. Power-Valid Upper-Limit Register Field Descriptions

Bit

Field

Type

Reset

Description

SIGN

Power-valid upper-limit data bits

14-3

PVU11-0

R/W

4E2h

Power-valid upper-limit data bits

2-0

Reserved

R/W

Reserved

7.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]

This register contains the value used to determine if any of the bus-voltage channels drops below the power-

valid lower-limit when the power-valid conditions are met. This limit contains the value used to compare all

bus-channel readings to verify that all channels remain above the power-valid lower-limit, thus maintaining

the power-valid condition. If any bus-voltage channel drops below the power-valid lower-limit, the PV alert pin

pulls low to indicate that the INA3221 detects a bus voltage reading below the power-valid lower-limit. For the

power-valid condition to be monitored, the bus measurements must be enabled through the mode (MODE3-1)

bits set in the Configuration register. The power-valid lower-limit LSB value is 8mV. Power-on reset value is

2328h = 9.000V.

Table 7-39. Power-Valid Lower-Limit Register

SIGN

PVL11 PVL10

PVL9

PVL8

PVL7

PVL6

PVL5

PVL4

PVL3

PVL2

PVL1

PVL0

—

R-0

RW-0

RW-1

RW-0

RW-1

RW-0

RW-1

RW-0

RW-1

RW-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7-40. Power-Valid Lower-Limit Register Field Descriptions

Bit

Field

Type

Reset

Description

SIGN

Power-valid lower-limit data bits

14-3

PVL11-0

R/W

465h

Power-valid lower-limit data bits

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INA3221

SBOS576C – MAY 2012 – REVISED SEPTEMBER 2025

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