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EXAMPLE BOARD LAYOUT

.000 PKG

0

8X (0.6)

13X (0.7)

9X (0.3)

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

2X (

)

2.4

2X (

)

1.45

(

)

0.85

2X (

)

0.25

2X (

)

0.35

(

)

1.65

2X (

)

2.4

2X (

)

1.4

(

)

1.4

5X (

)

3.2

5X (

)

3.2

(

)

0.95

2X ( )

2

2X ( )

2

( 0.2) TYP

VIA

(R0.05) TYP

4X (0.4)

10X (0.3)

VQFN - 1 mm max height

DEK0015A

PLASTIC QUAD FLAT PACK - NO LEAD

4228519/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK DETAILS

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE 12.000

1

7

8

9

14

15

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

METAL UNDER

SOLDER MASK

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

DEFINED

INA790A, INA790B

SBOSAA6B – MAY 2024 – REVISED JULY 2025

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34

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