ISO1430DWR datasheet(34/49 Pages) TI2

34 / 49 page

12 Layout

12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 12-2). Layer stacking

must be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-

frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of the

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in2.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

Section 12.2 shows the recommended placement and routing of the device bypass capacitors and optional TVS

diodes. Put the VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not use

vias to complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal layer

is needed, add a second power or ground plane system to the stack to keep the it symmetrical. This makes the

stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system

can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Refer to the Digital Isolator Design Guide for detailed layout recommendations.

12.1.1 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace

lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper

alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength

and stiffness, and the self-extinguishing flammability-characteristics.

12.2 Layout Example

10 mils

40 mils

FR-4

0r ~ 4.5

Keep this space

free from planes,

traces, pads, and

vias

Ground plane

Power plane

Low-speed traces

High-speed traces

Figure 12-1. Recommended Layer Stack

ISO1450, ISO1452, ISO1410, ISO1412, ISO1430, ISO1432

SLLSF22H – APRIL 2018 – REVISED JUNE 2024

www.ti.com

Submit Document Feedback

Product Folder Links: ISO1450 ISO1452 ISO1410 ISO1412 ISO1430 ISO1432

ISO1430DWR Datasheet(PDF) 34 Page - Texas Instruments

ISO1430DWR Datasheet(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL