LF412QML

www.ti.com

SNOSAO7A – DECEMBER 2010 – REVISED MARCH 2013

APPLICATION HINTS

The LF412 JFET input dual op amp is internally trimmed ( BI-FET II™) providing very low input offset voltages

and ensured input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source

and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily

be accommodated without a large increase in input current. The maximum differential input voltage is

independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the

negative supply as this will cause large currents to flow which can result in a destroyed unit.

Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and

force the amplifier output to the corresponding high or low state.

Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In

neither case does a latch occur since raising the input back within the common-mode range again puts the input

stage and thus the amplifier in a normal operating mode.

Exceeding the positive common-mode limit on a single input will not change the phase of the output, however, if

both inputs exceed the limit, the output of the amplifier may be forced to a high state.

The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain

bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings

to within 3V of the negative supply, an increase in input offset voltage may occur.

Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±6.0V power

supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate.

The amplifiers will drive a 2 k

Ω load resistance to ±10V over the full temperature range. If the amplifier is forced

to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage

swing and finally reach an active current limit on both positive and negative swings.

Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in

polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through

the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed

unit.

As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in

order to ensure stability. For example, resistors from the output to an input should be placed with the body close

to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the

capacitance from the input to ground.

A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and

capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.

In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed

loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less

than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the

input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor

and the resistance it parallels is greater than or equal to the original feedback pole time constant.

Copyright © 2010–2013, Texas Instruments Incorporated

Submit Documentation Feedback

11

Product Folder Links: LF412QML