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EXAMPLE BOARD LAYOUT

.003 MAX

[0.07]

ALL AROUND

.003 MIN

[0.07]

ALL AROUND

3X (.110)

[2.8]

3X (.039)

[1]

2X (.100 )

[2.54]

(.305 )

[7.74]

(.059 )

[1.49]

(.479

)

[12.16]

(.229 )

[5.81]

(.400

)

[10.16]

(.328 )

[8.32]

(R.002 ) TYP

[0.05]

(.002 )

[0.05]

2X

(.054 )

[1.37]

(.177)

[4.5]

4X (.047)

[1.2]

(

.008) TYP VIA

[0.2]

8X (.046 )

[1.18]

6X (.050 )

[1.27]

4219861/A 01/2022

TO-220 - 4.69 mm max height

NDG0003F

TRANSISTOR OUTLINE

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOTES: (continued)

3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers

SLMA002(www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004).

4. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 5X

PKG

PKG

SYMM

1

2

3

METAL EDGE

SOLDER MASK

OPENING

EXPOSED

METAL

METAL UNDER

SOLDER MASK

SOLDER MASK

OPENING

EXPOSED

METAL