LPC2212 datasheet(23/45 Pages) PHILIPS

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LPC2212_2214_4

Product data sheet

Rev. 04 — 3 January 2008

23 of 45

NXP Semiconductors

LPC2212/2214

16/32-bit ARM microcontrollers

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2212/2214 allows the user to enable different levels of security in

the system so that access to the on-chip ﬂash and use of the JTAG and ISP can be

restricted. When needed, CRP is invoked by programming a speciﬁc pattern into a

dedicated ﬂash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding

ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and ﬂash ﬁeld updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It

is up to the user’s application to provide (if needed) ﬂash update mechanism using IAP

calls or call reinvoke ISP command to enable ﬂash update via UART0.

Remark: Devices without the sufﬁx /00 or /01 have only a security level equivalent to

CRP2 available.

6.18.5 External interrupt inputs

The LPC2212/2214 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake up the processor from Power-down mode.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

LPC2212 Datasheet(PDF) 23 Page - NXP Semiconductors

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