SPC563M64L7 datasheet(16/128 Pages) STMICROELECTRONICS

16 / 128 page

Overview

SPC563M64x, SPC563M60x

16/128

DocID14642 Rev 12

– Instruction set enhancements for smaller more flexible code generation

– Programmable channel mode for customization of channel operation



Enhanced queued A/D converter (eQADC)

–

Two independent on-chip redundant signed digit (RSD) cyclic ADCs

8-, 10-, and 12-bit resolution

– Differential conversions

– Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and

8-bit accuracy at 1 MSample/s (ADC_CLK = 15 MHz) for differential

conversions

– Differential channels include variable gain amplifier (VGA) for improved

dynamic range (

1; 2; 4)

– Differential channels include programmable pull-up and pull-down resistors

for biasing and sensor diagnostics (200 k

; 100 k; low value of 5 k)

– Single-ended signal range from 0 to 5 V

– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

– Provides time stamp information when requested

– Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs

(RFIFOs)

– Supports both right-justified unsigned and signed formats for conversion

results

– Temperature sensor to enable measurement of die temperature

– Ability to measure all power supply pins directly

–

Automatic application of ADC calibration constants

– Provision of reference voltages (25% VREF and 75% VREF) for ADC

calibration purposes

–

Up to 34(b) input channels available to the two on-chip ADCs

–

Four pairs of differential analog input channels

–

Full duplex synchronous serial interface to an external device

– Has a free-running clock for use by the external device

– Supports a 26-bit message length

– Transmits a null message when there are no triggered CFIFOs with

commands bound for external CBuffers, or when there are triggered CFIFOs

with commands bound for external CBuffers but the external CBuffers are full

–

Parallel Side Interface to communicate with an on-chip companion module

–

Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be

aborted and the queued conversions in the CBUFFER to be bypassed. Delay from

Trigger to start of conversion is 13 system clocks + 1 ADC clock.)

–

eQADC Result Streaming. Generation of a continuous stream of ADC conversion

results from a single eQADC command word. Controlled by two different trigger

signals; one to define the rate at which results are generated and the other to

define the beginning and ending of the stream. Used to digitize waveforms during

specific time/angle windows, e.g., engine knock sensor sampling.

176-pin package has 34 input channels; 144-pin package has 32 input channels; 100-pin package has 23 input

channels.

SPC563M64L7 Datasheet(PDF) 16 Page - STMicroelectronics

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