LMX2572LP datasheet(13/83 Pages) TI2

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Pre-R

Divider

Multiplier

Post-R

Divider

OSCin

Phase

Frequency

Detector

Doubler

LMX2572LP

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SNAS764 – MAY 2018

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Feature Description (continued)

Figure 21. Reference Path

The Doubler allows one to double the input reference frequency up to 250 MHz. The Doubler adds minimal noise

and is useful for raising the phase detector frequency for better phase noise. The Doubler can also be used to

avoid spurs. The Doubler uses both the rising and falling edges of the input signal, so the input signal must have

50% duty cycle if the Doubler is enabled. Note that the Multiplier cannot be used if the Doubler is engaged.

The Pre-R divider can help reduce input frequency so that the Multiplier can be used and the maximum 200-MHz

input frequency limitation of the Post-R divider can be met.

The Multiplier multiplies the frequency up under the allowable multiplications of 3, 4, 5, 6, and 7. In combination

with the Pre-R and Post-R dividers, the Multiplier offers the flexibility to shift the phase detector frequency away

from frequencies that may create integer boundary spurs with the VCO and the output frequencies. Be aware

that unlike the Doubler, the Multiplier degrades the PLL figure of merit. This degradation would only matter,

however, for a very clean reference oscillator input and if the loop bandwidth was wide. The user should not use

the Doubler while using the Multiplier. The Multiplier is bypassed if its value is set to 1.

The Post-R divider can be used to further divide down the frequency to the phase detector frequency. When it is

used (PLL_R > 1), the input frequency to this divider is limited to 200 MHz.

Use Equation 1 to calculate the phase detector frequency, fPD.

fPD = fOSCin × OSC_2X × MULT / (PLL_R_PRE × PLL_R)

(1)

Table 1 summarizes the usage boundaries of these functional blocks in the reference path.

Table 1. Reference Path Boundaries

PARAMETER

VALUE

INPUT

FREQUENCY

(MHz)

OUTPUT

FREQUENCY

(MHz)

NOTES

MIN

MAX

MIN

MAX

OSCin

N/A

250

Doubler

0 (Bypassed), 1 (x2)

125

250

When OSC_2X = 1, Multiplier cannot be used at the same

time.

Pre-R divider

1 (Bypassed), 2, 3, …, 254, 255

200

0.25

200

Keep it equals 1 unless when necessary.

Multiplier

1 (Bypassed), 3, 4, 5, 6, 7

150

When the output frequency is greater than 100MHz, set

MULT_HI = 1.

Post-R divider

1 (Bypass), 2, 3, …, 254, 255

200

0.25

200

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-R divider and N divider and generates a correction current

corresponding to the phase error until the two signals are aligned in phase. This charge-pump current is software

programmable to many different levels, allowing modification of the closed-loop bandwidth of the PLL.

Table 2. Charge Pump Gain

CGP

4 or 8

5 or 9

6 or 10

7 or 11

UNIT

Gain

Tri-state

625

1250

1875

2500

3125

3750

4375

5000

5625

6250

6875

µA

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