ETC5054 datasheet(5/18 Pages) STMICROELECTRONICS

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edges clock out the remaining seven bits. The DX

output is disabled by the falling BCLKX edge fol-

lowing the eighth rising edge, or by FSX going

low, which-ever comes later. A rising edge on the

receive frame sync pulse, FSR, will cause the

PCM data at DR to be latched in on the next eight

falling edges of BCLKR (BCLKX in synchronous

mode). Both devices may utilize the long frame

sync pulse in synchronous or asynchronous

mode.

TRANSMIT SECTION

The transmit section input is an operational ampli-

fier with provision for gain adjustment using two

external resistors, see figure 6. The low noise and

wide bandwidth allow gains in excess of 20 dB

across the audio passband to be realized. The op

amp drives a unitygain filter consisting of RD ac-

tive pre-filter,

followed by an

eighth order

switched-capacitor bandpass filter clocked at 256

kHz. The output of this filter directly drives the en-

coder sample-and-hold circuit. The A/D is of com-

panding type according to A-law (ETC5057) or

µ–

law (ETC5054) coding conventions. A precision

voltage reference is trimmed in manufacturing to

provide an input overload (tMAX) of nominally 2.5V

peak (see table of transmission characteristics).

The FSX frame sync pulse controls the sampling

of the filter output, and then the successive-ap-

proximation encoding cycle begins. The 8-bit

code is then loaded into a buffer and shifted out

through DX at the next FSX pulse. The total en-

coding delay will be approximately 165

µs (due to

the transmit filter) plus 125

µs (due to encoding

delay), which totals 290

µs. Any offset vol-tage

due to the filters or comparator is cancelled by

sign bit integration.

RECEIVE SECTION

The receive section consists of an expanding

DAC which drives a fifth order switched-capacitor

low pass filter clocked at 256 kHz. The decoder is

A-law (ETC5057) or

µ–law (ETC5054) and the

5th order low pass filter corrects for the sin x/x at-

tenuation due to the 8 kHz sample and hold.

The filter is then followed by a 2nd order RC ac-

tive post-filter and power amplifier capable of driv-

ing a 600

Ω load to a level of 7.2 dBm. The re-

ceive section is unity-gain. Upon the occurence of

FSR, the data at the DR input is clocked in on the

falling edge of the next eight BCLKR (BCLKX)pe-

riods. At the end of the decoder time slot, the de-

coding cycle begins, and 10

µs later the decoder

DAC output is updated. The total decoder delay

∼ 10µs (decoder update) plus 110µs (filter

delay) plus 62.5

µs (1/2 frame), which gives ap-

proximately 180

µs. A mute circuitry is a active

during 10ms when power up.

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

VCC

VCC to GNDA

VBB

VBB to GNDA

– 7

VIN,VOUT

Voltage at any Analog Input or Output

VCC + 0.3 to VBB – 0.3

Voltage at Any Digital Input or Output

VCC + 0.3 to GNDA – 0.3

Toper

Operating Temperature Range

– 25 to + 125

°C

Tstg

Storage Temperature Range

– 65 to + 150

°C

Lead Temperature (soldering, 10 seconds)

300

°C

ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V

± 5%, VBB = – 5.0 V ± 5%GNDA = 0 V,

TA =0

°Cto70 °C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA =25 °C ; all signals

are referenced to GNDA.

Symbol

Parameter

Min.

Typ.

Max.

Unit

VIL

Input Low Voltage

0.6

VIH

Input High Voltage

2.2

VOL

Output Low Voltage

IL = 3.2mA

D X

IL = 3.2mA, Open Drain

TSX

0.4

VOH

Output High Voltage

IH = 3.2mA

D X

2.4

IIL

Input Low Current (GNDA

≤ VIN ≤ VIL, all digital inputs)

–10

µA

IIH

Input High Current (VIH

≤ VIN ≤ VCC) except BCLKR/BCLKSEL

–10

µA

IOZ

Output Current in HIGH Impedance State (TRI-STATE)

(GNDA

≤ VO ≤ VCC)D X

–10

µA

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