SN74LVC1G34DBVT datasheet(14/54 Pages) TI2

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8.2.1.4 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Verify that the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will

optimize performance. This can be accomplished by providing short, appropriately sized traces from the

SN74LVC1G34 to one or more of the receiving devices.

3. Verify that the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this prevents the maximum

output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive

load measured in MΩ; much larger than the minimum calculated previously.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the CMOS Power Consumption and Cpd Calculation

application note.

8.2.2 Application Curves

Frequency - MHz

D003

Icc 1.8V

Icc 2.5V

Icc 3.3V

Icc 5V

Figure 8-1. Icc vs Frequency

SN74LVC1G34

SCES519O – DECEMBER 2003 – REVISED OCTOBER 2025

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SN74LVC1G34DBVT Datasheet(PDF) 14 Page - Texas Instruments