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SN74LVC1G97DBVR Datasheet(PDF) 13 Page - Texas Instruments |
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SN74LVC1G97DBVR Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 40 page ![]() Vcc Unused Input Input Output Input Unused Input Output 13 SN74LVC1G97 www.ti.com SCES416N – DECEMBER 2002 – REVISED JANUARY 2017 Product Folder Links: SN74LVC1G97 Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated 11 Layout 11.1 Layout Guidelines When using multiple-bit logic devices, inputs must never float. In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected, because the undefined voltages at the outside connections result in undefined operational states. Figure 13 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when disabled. 11.2 Layout Example Figure 13. Layout Diagrams |
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