TAS5713PHPR.A datasheet(7/72 Pages) TI2

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TAS5713

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SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010

PIN FUNCTIONS (continued)

5-V

TYPE(1)

TERMINATION(2)

DESCRIPTION

TOLERANT

NAME

NO.

DVSSO

Oscillator ground

GND

Analog ground for power stage

GVDD_OUT

Gate drive internal regulator output

LRCLK

5-V

Pulldown

Input serial audio data left/right clock (sample-rate clock)

MCLK

5-V

Pulldown

Master clock input

5, 7

–

No connect

OSC_RES

Oscillator trim resistor. Connect an 18.2-k

Ω, 1% resistor to DVSSO.

OUT_A

Output, half-bridge A

OUT_B

Output, half-bridge B

OUT_C

Output, half-bridge C

OUT_D

Output, half-bridge D

PBTL

Low means BTL or SE mode; high means PBTL mode. Information

goes directly to power stage.

PDN

5-V

Pullup

Power down, active-low. PDN prepares the device for loss of power

supplies by shutting down the noise shaper and initiating the PWM

stop sequence.

PGND_AB

47, 48

Power ground for half-bridges A and B

PGND_CD

37, 38

Power ground for half-bridges C and D

PLL_FLTM

PLL negative loop-filter terminal

PLL_FLTP

PLL positive loop-filter terminal

PVDD_A

2, 3

Power-supply input for half-bridge output A

PVDD_B

44, 45

Power-supply input for half-bridge output B

PVDD_C

40, 41

Power-supply input for half-bridge output C

PVDD_D

34, 35

Power-supply input for half-bridge output D

RESET

5-V

Pullup

Reset, active-low. A system reset is generated by applying a logic

low to this pin. RESET is an asynchronous control signal that

restores the DAP to its default conditions and places the PWM in the

hard-mute (high-impedance) state.

SCL

5-V

I2C serial control clock input

SCLK

5-V

Pulldown

Serial audio-data clock (shift clock). SCLK is the serial-audio-port

input-data bit clock.

SDA

DIO

5-V

I2C serial control data interface input/output

SDIN

5-V

Pulldown

Serial audio data input. SDIN supports three discrete (stereo) data

formats.

SSTIMER

Controls ramp time of OUT_x to minimize pop. Leave this pin

floating for BD mode. Requires capacitor of 2.2 nF to GND in AD

mode. The capacitor determines the ramp time.

STEST

Factory test pin. Connect directly to DVSS.

VR_ANA

Internally regulated 1.8-V analog supply voltage. This pin must not

be used to power external devices.

VR_DIG

Internally regulated 1.8-V digital supply voltage. This pin must not be

used to power external devices.

VREG

Digital regulator output. Not to be used for powering external

circuitry.

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