TLV9062IDRG4 datasheet(22/97 Pages) TI2

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Table 6-1. TLV906x EMIRR IN+ For Frequencies of Interest (continued)

FREQUENCY

APPLICATION or ALLOCATION

EMIRR IN+

3.6GHz

Radiolocation, aero communication and navigation, satellite, mobile, S-band

88.8dB

5GHz

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4GHz to 8GHz)

87.6dB

6.3.4 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated

state to a linear state. The output devices of the operational amplifier enter a saturation region when the output

voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device

enters the saturation region, the charge carriers in the output devices require time to return to the linear state.

After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,

the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew

time. The overload recovery time for the TLV906x family is approximately 200ns.

6.3.5 Shutdown Function

The TLV906xS devices feature SHDN pins that disable the op amp, placing the op amp into a low-power

standby mode. In this mode, the op amp typically consumes less than 1µA. The SHDN pins are active-low,

meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown

feature lies around 800mV (typical) and does not change with respect to the supply voltage. Hysteresis has

been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown

behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage

between V– and V– + 0.2V. A valid logic high is defined as a voltage between V– + 1.2V and V+. The shutdown

pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit. There is

no internal pull-up to enable the amplifier.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and

quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature

may be used to greatly reduce the average current and extend battery life. The enable time is 10µs for full

shutdown of all channels; disable time is 6µs. When disabled, the output assumes a high-impedance state.

This architecture allows the TLV906xS to operate as a gated amplifier (or to have the device output multiplexed

onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load

resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10kΩ load to

midsupply (VS / 2) is required. If using the TLV906xS without a load, the resulting turnoff time is significantly

increased.

6.4 Device Functional Modes

The TLV906x family are operational when the power-supply voltage is between 1.8V (±0.9V) and 5.5V (±2.75V).

The TLV906xS devices feature a shutdown mode and are shut down when a valid logic low is applied to the

shutdown pin.

TLV9061, TLV9062, TLV9064

SBOS839M – MARCH 2017 – REVISED DECEMBER 2024

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