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TPA3136D2 Datasheet(PDF) 16 Page - Texas Instruments |
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TPA3136D2 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 41 page  7.2 Functional Block Diagram PWM Logic Gate Drive Gate Drive PVCC PVCC GVDD PVCC PVCC BSPL GND OUTPL OUTNL GND GVDD BSNL PWM Logic Gate Drive Gate Drive PVCC PVCC GVDD PVCC PVCC BSNR GND OUTNR OUTPR GND GVDD BSPR LINP LINN RINP RINN UVLO/OVLO SC Detect DC Detect Thermal Detect Startup Protection Logic Biases and References SD/FAULT SD GAIN_SEL MOD_SEL AVCC TTL Buffer Ramp Generator AVDD GVDD GVDD LDO Regulator Gain Control PLIMIT Spread Spectrum Control Gain Control Modulation Scheme and PBTL Select Modulation Scheme and PBTL Select OUTPL FB OUTNL FB OUTNR FB OUTPR FB OUTPR FB OUTNR FB OUTNL FB OUTPL FB PLIMIT PLIMIT LIMITER Reference UVLO Select FAULT Gain Control Modulation scheme /UVLO Select Input Sense PBTL Select GND MUTE TPA3139D2 SLOS810A – OCTOBER 2019 – REVISED AUGUST 2020 www.ti.com 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPA3139D2 |
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